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1 From 028f5f8ef44fcf87a456772cbb9f0d90a0a22884 Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Fri, 14 May 2021 22:59:55 +0200
4 Subject: [PATCH] net: dsa: qca8k: handle error with qca8k_read operation
5
6 qca8k_read can fail. Rework any user to handle error values and
7 correctly return.
8
9 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
10 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
11 Signed-off-by: David S. Miller <davem@davemloft.net>
12 ---
13 drivers/net/dsa/qca8k.c | 73 ++++++++++++++++++++++++++++++++---------
14 1 file changed, 58 insertions(+), 15 deletions(-)
15
16 --- a/drivers/net/dsa/qca8k.c
17 +++ b/drivers/net/dsa/qca8k.c
18 @@ -231,8 +231,13 @@ static int
19 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
20 {
21 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
22 + int ret;
23 +
24 + ret = qca8k_read(priv, reg);
25 + if (ret < 0)
26 + return ret;
27
28 - *val = qca8k_read(priv, reg);
29 + *val = ret;
30
31 return 0;
32 }
33 @@ -300,15 +305,20 @@ qca8k_busy_wait(struct qca8k_priv *priv,
34 return ret;
35 }
36
37 -static void
38 +static int
39 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
40 {
41 - u32 reg[4];
42 + u32 reg[4], val;
43 int i;
44
45 /* load the ARL table into an array */
46 - for (i = 0; i < 4; i++)
47 - reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
48 + for (i = 0; i < 4; i++) {
49 + val = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
50 + if (val < 0)
51 + return val;
52 +
53 + reg[i] = val;
54 + }
55
56 /* vid - 83:72 */
57 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
58 @@ -323,6 +333,8 @@ qca8k_fdb_read(struct qca8k_priv *priv,
59 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
60 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
61 fdb->mac[5] = reg[0] & 0xff;
62 +
63 + return 0;
64 }
65
66 static void
67 @@ -374,6 +386,8 @@ qca8k_fdb_access(struct qca8k_priv *priv
68 /* Check for table full violation when adding an entry */
69 if (cmd == QCA8K_FDB_LOAD) {
70 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
71 + if (reg < 0)
72 + return reg;
73 if (reg & QCA8K_ATU_FUNC_FULL)
74 return -1;
75 }
76 @@ -388,10 +402,10 @@ qca8k_fdb_next(struct qca8k_priv *priv,
77
78 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
79 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
80 - if (ret >= 0)
81 - qca8k_fdb_read(priv, fdb);
82 + if (ret < 0)
83 + return ret;
84
85 - return ret;
86 + return qca8k_fdb_read(priv, fdb);
87 }
88
89 static int
90 @@ -449,6 +463,8 @@ qca8k_vlan_access(struct qca8k_priv *pri
91 /* Check for table full violation when adding an entry */
92 if (cmd == QCA8K_VLAN_LOAD) {
93 reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1);
94 + if (reg < 0)
95 + return reg;
96 if (reg & QCA8K_VTU_FUNC1_FULL)
97 return -ENOMEM;
98 }
99 @@ -475,6 +491,8 @@ qca8k_vlan_add(struct qca8k_priv *priv,
100 goto out;
101
102 reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);
103 + if (reg < 0)
104 + return reg;
105 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
106 reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
107 if (untagged)
108 @@ -506,6 +524,8 @@ qca8k_vlan_del(struct qca8k_priv *priv,
109 goto out;
110
111 reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);
112 + if (reg < 0)
113 + return reg;
114 reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
115 reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
116 QCA8K_VTU_FUNC0_EG_MODE_S(port);
117 @@ -621,8 +641,11 @@ qca8k_mdio_read(struct qca8k_priv *priv,
118 QCA8K_MDIO_MASTER_BUSY))
119 return -ETIMEDOUT;
120
121 - val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) &
122 - QCA8K_MDIO_MASTER_DATA_MASK);
123 + val = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL);
124 + if (val < 0)
125 + return val;
126 +
127 + val &= QCA8K_MDIO_MASTER_DATA_MASK;
128
129 return val;
130 }
131 @@ -978,6 +1001,8 @@ qca8k_phylink_mac_link_state(struct dsa_
132 u32 reg;
133
134 reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port));
135 + if (reg < 0)
136 + return reg;
137
138 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
139 state->an_complete = state->link;
140 @@ -1078,18 +1103,26 @@ qca8k_get_ethtool_stats(struct dsa_switc
141 {
142 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
143 const struct qca8k_mib_desc *mib;
144 - u32 reg, i;
145 + u32 reg, i, val;
146 u64 hi;
147
148 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
149 mib = &ar8327_mib[i];
150 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
151
152 - data[i] = qca8k_read(priv, reg);
153 + val = qca8k_read(priv, reg);
154 + if (val < 0)
155 + continue;
156 +
157 if (mib->size == 2) {
158 hi = qca8k_read(priv, reg + 4);
159 - data[i] |= hi << 32;
160 + if (hi < 0)
161 + continue;
162 }
163 +
164 + data[i] = val;
165 + if (mib->size == 2)
166 + data[i] |= hi << 32;
167 }
168 }
169
170 @@ -1107,18 +1140,25 @@ qca8k_set_mac_eee(struct dsa_switch *ds,
171 {
172 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
173 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
174 + int ret = 0;
175 u32 reg;
176
177 mutex_lock(&priv->reg_mutex);
178 reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
179 + if (reg < 0) {
180 + ret = reg;
181 + goto exit;
182 + }
183 +
184 if (eee->eee_enabled)
185 reg |= lpi_en;
186 else
187 reg &= ~lpi_en;
188 qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
189 - mutex_unlock(&priv->reg_mutex);
190
191 - return 0;
192 +exit:
193 + mutex_unlock(&priv->reg_mutex);
194 + return ret;
195 }
196
197 static int
198 @@ -1456,6 +1496,9 @@ qca8k_sw_probe(struct mdio_device *mdiod
199
200 /* read the switches ID register */
201 id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
202 + if (id < 0)
203 + return id;
204 +
205 id >>= QCA8K_MASK_CTRL_ID_S;
206 id &= QCA8K_MASK_CTRL_ID_M;
207 if (id != QCA8K_ID_QCA8337)
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