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1 From b3b3cd885ed39cb4b38319a1c4fa4e41db6fee72 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
3 Date: Mon, 15 May 2023 17:19:20 +0200
4 Subject: [PATCH] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ /
5 MIT
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing.
11 That syncs more Northstar code to be based on the same licensing schema.
12
13 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
14 Cc: Hauke Mehrtens <hauke@hauke-m.de>
15 Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
16 Link: https://lore.kernel.org/r/20230515151921.25021-1-zajec5@gmail.com
17 Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
18 ---
19 arch/arm/boot/dts/bcm-ns.dtsi | 90 +++++++++++++++++++++++++++++++++
20 arch/arm/boot/dts/bcm5301x.dtsi | 85 -------------------------------
21 2 files changed, 90 insertions(+), 85 deletions(-)
22
23 --- a/arch/arm/boot/dts/bcm-ns.dtsi
24 +++ b/arch/arm/boot/dts/bcm-ns.dtsi
25 @@ -1,4 +1,7 @@
26 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
27 +/*
28 + * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
29 + */
30
31 #include <dt-bindings/clock/bcm-nsp.h>
32 #include <dt-bindings/gpio/gpio.h>
33 @@ -7,6 +10,81 @@
34 #include <dt-bindings/interrupt-controller/arm-gic.h>
35
36 / {
37 + interrupt-parent = <&gic>;
38 + #address-cells = <1>;
39 + #size-cells = <1>;
40 +
41 + chipcommon-a-bus@18000000 {
42 + compatible = "simple-bus";
43 + ranges = <0x00000000 0x18000000 0x00001000>;
44 + #address-cells = <1>;
45 + #size-cells = <1>;
46 +
47 + uart0: serial@300 {
48 + compatible = "ns16550";
49 + reg = <0x0300 0x100>;
50 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
51 + clocks = <&iprocslow>;
52 + status = "disabled";
53 + };
54 +
55 + uart1: serial@400 {
56 + compatible = "ns16550";
57 + reg = <0x0400 0x100>;
58 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
59 + clocks = <&iprocslow>;
60 + pinctrl-names = "default";
61 + pinctrl-0 = <&pinmux_uart1>;
62 + status = "disabled";
63 + };
64 + };
65 +
66 + mpcore-bus@19000000 {
67 + compatible = "simple-bus";
68 + ranges = <0x00000000 0x19000000 0x00023000>;
69 + #address-cells = <1>;
70 + #size-cells = <1>;
71 +
72 + scu@20000 {
73 + compatible = "arm,cortex-a9-scu";
74 + reg = <0x20000 0x100>;
75 + };
76 +
77 + timer@20200 {
78 + compatible = "arm,cortex-a9-global-timer";
79 + reg = <0x20200 0x100>;
80 + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
81 + clocks = <&periph_clk>;
82 + };
83 +
84 + timer@20600 {
85 + compatible = "arm,cortex-a9-twd-timer";
86 + reg = <0x20600 0x20>;
87 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
88 + IRQ_TYPE_EDGE_RISING)>;
89 + clocks = <&periph_clk>;
90 + };
91 +
92 + gic: interrupt-controller@21000 {
93 + compatible = "arm,cortex-a9-gic";
94 + #interrupt-cells = <3>;
95 + #address-cells = <0>;
96 + interrupt-controller;
97 + reg = <0x21000 0x1000>,
98 + <0x20100 0x100>;
99 + };
100 +
101 + L2: cache-controller@22000 {
102 + compatible = "arm,pl310-cache";
103 + reg = <0x22000 0x1000>;
104 + cache-unified;
105 + arm,shared-override;
106 + prefetch-data = <1>;
107 + prefetch-instr = <1>;
108 + cache-level = <2>;
109 + };
110 + };
111 +
112 axi@18000000 {
113 compatible = "brcm,bus-axi";
114 reg = <0x18000000 0x1000>;
115 @@ -216,6 +294,18 @@
116 };
117 };
118
119 + nand_controller: nand-controller@18028000 {
120 + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
121 + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
122 + reg-names = "nand", "iproc-idm", "iproc-ext";
123 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
124 +
125 + #address-cells = <1>;
126 + #size-cells = <0>;
127 +
128 + brcm,nand-has-wp;
129 + };
130 +
131 thermal-zones {
132 cpu_thermal: cpu-thermal {
133 polling-delay-passive = <0>;
134 --- a/arch/arm/boot/dts/bcm5301x.dtsi
135 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
136 @@ -11,41 +11,7 @@
137 #include "bcm-ns.dtsi"
138
139 / {
140 - #address-cells = <1>;
141 - #size-cells = <1>;
142 - interrupt-parent = <&gic>;
143 -
144 - chipcommon-a-bus@18000000 {
145 - compatible = "simple-bus";
146 - ranges = <0x00000000 0x18000000 0x00001000>;
147 - #address-cells = <1>;
148 - #size-cells = <1>;
149 -
150 - uart0: serial@300 {
151 - compatible = "ns16550";
152 - reg = <0x0300 0x100>;
153 - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
154 - clocks = <&iprocslow>;
155 - status = "disabled";
156 - };
157 -
158 - uart1: serial@400 {
159 - compatible = "ns16550";
160 - reg = <0x0400 0x100>;
161 - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
162 - clocks = <&iprocslow>;
163 - pinctrl-names = "default";
164 - pinctrl-0 = <&pinmux_uart1>;
165 - status = "disabled";
166 - };
167 - };
168 -
169 mpcore-bus@19000000 {
170 - compatible = "simple-bus";
171 - ranges = <0x00000000 0x19000000 0x00023000>;
172 - #address-cells = <1>;
173 - #size-cells = <1>;
174 -
175 a9pll: arm_clk@0 {
176 #clock-cells = <0>;
177 compatible = "brcm,nsp-armpll";
178 @@ -53,26 +19,6 @@
179 reg = <0x00000 0x1000>;
180 };
181
182 - scu@20000 {
183 - compatible = "arm,cortex-a9-scu";
184 - reg = <0x20000 0x100>;
185 - };
186 -
187 - timer@20200 {
188 - compatible = "arm,cortex-a9-global-timer";
189 - reg = <0x20200 0x100>;
190 - interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
191 - clocks = <&periph_clk>;
192 - };
193 -
194 - timer@20600 {
195 - compatible = "arm,cortex-a9-twd-timer";
196 - reg = <0x20600 0x20>;
197 - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
198 - IRQ_TYPE_EDGE_RISING)>;
199 - clocks = <&periph_clk>;
200 - };
201 -
202 watchdog@20620 {
203 compatible = "arm,cortex-a9-twd-wdt";
204 reg = <0x20620 0x20>;
205 @@ -80,25 +26,6 @@
206 IRQ_TYPE_EDGE_RISING)>;
207 clocks = <&periph_clk>;
208 };
209 -
210 - gic: interrupt-controller@21000 {
211 - compatible = "arm,cortex-a9-gic";
212 - #interrupt-cells = <3>;
213 - #address-cells = <0>;
214 - interrupt-controller;
215 - reg = <0x21000 0x1000>,
216 - <0x20100 0x100>;
217 - };
218 -
219 - L2: cache-controller@22000 {
220 - compatible = "arm,pl310-cache";
221 - reg = <0x22000 0x1000>;
222 - cache-unified;
223 - arm,shared-override;
224 - prefetch-data = <1>;
225 - prefetch-instr = <1>;
226 - cache-level = <2>;
227 - };
228 };
229
230 pmu {
231 @@ -301,18 +228,6 @@
232 };
233 };
234
235 - nand_controller: nand-controller@18028000 {
236 - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
237 - reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
238 - reg-names = "nand", "iproc-idm", "iproc-ext";
239 - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
240 -
241 - #address-cells = <1>;
242 - #size-cells = <0>;
243 -
244 - brcm,nand-has-wp;
245 - };
246 -
247 spi@18029200 {
248 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
249 reg = <0x18029200 0x184>,
Staging tree of Christian Marangi