git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From d34db686a3d74bd564bfce2ada15011c556269fc Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Tue, 10 Sep 2024 06:40:23 +0200
   4 Subject: [PATCH 2/3] clk: ralink: mtmips: fix clocks probe order in oldest
   5  ralink SoCs
   6
   7 Base clocks are the first in being probed and are real dependencies of the
   8 rest of fixed, factor and peripheral clocks. For old ralink SoCs RT2880,
   9 RT305x and RT3883 'xtal' must be defined first since in any other case,
  10 when fixed clocks are probed they are delayed until 'xtal' is probed so the
  11 following warning appears:
  12
  13  WARNING: CPU: 0 PID: 0 at drivers/clk/ralink/clk-mtmips.c:499 rt3883_bus_recalc_rate+0x98/0x138
  14  Modules linked in:
  15  CPU: 0 PID: 0 Comm: swapper Not tainted 6.6.43 #0
  16  Stack : 805e58d0 00000000 00000004 8004f950 00000000 00000004 00000000 00000000
  17  80669c54 80830000 80700000 805ae570 80670068 00000001 80669bf8 00000000
  18  00000000 00000000 805ae570 80669b38 00000020 804db7dc 00000000 00000000
  19  203a6d6d 80669b78 80669e48 70617773 00000000 805ae570 00000000 00000009
  20  00000000 00000001 00000004 00000001 00000000 00000000 83fe43b0 00000000
  21  ...
  22  Call Trace:
  23  [<800065d0>] show_stack+0x64/0xf4
  24  [<804bca14>] dump_stack_lvl+0x38/0x60
  25  [<800218ac>] __warn+0x94/0xe4
  26  [<8002195c>] warn_slowpath_fmt+0x60/0x94
  27  [<80259ff8>] rt3883_bus_recalc_rate+0x98/0x138
  28  [<80254530>] __clk_register+0x568/0x688
  29  [<80254838>] of_clk_hw_register+0x18/0x2c
  30  [<8070b910>] rt2880_clk_of_clk_init_driver+0x18c/0x594
  31  [<8070b628>] of_clk_init+0x1c0/0x23c
  32  [<806fc448>] plat_time_init+0x58/0x18c
  33  [<806fdaf0>] time_init+0x10/0x6c
  34  [<806f9bc4>] start_kernel+0x458/0x67c
  35
  36  ---[ end trace 0000000000000000 ]---
  37
  38 When this driver was mainlined we could not find any active users of old
  39 ralink SoCs so we cannot perform any real tests for them. Now, one user
  40 of a Belkin f9k1109 version 1 device which uses RT3883 SoC appeared and
  41 reported some issues in openWRT:
  42 - https://github.com/openwrt/openwrt/issues/16054
  43
  44 Thus, define a 'rt2880_xtal_recalc_rate()' just returning the expected
  45 frequency 40Mhz and use it along the old ralink SoCs to have a correct
  46 boot trace with no warnings and a working clock plan from the beggining.
  47
  48 Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
  49 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  50 Link: https://lore.kernel.org/r/20240910044024.120009-3-sergio.paracuellos@gmail.com
  51 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  52 ---
  53  drivers/clk/ralink/clk-mtmips.c | 21 +++++++++++++--------
  54  1 file changed, 13 insertions(+), 8 deletions(-)
  55
  56 --- a/drivers/clk/ralink/clk-mtmips.c
  57 +++ b/drivers/clk/ralink/clk-mtmips.c
  58 @@ -263,10 +263,6 @@ err_clk_unreg:
  59                 .rate = _rate            \
  60         }
  61
  62 -static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
  63 -       CLK_FIXED("xtal", NULL, 40000000)
  64 -};
  65 -
  66  static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
  67         CLK_FIXED("xtal", NULL, 40000000),
  68         CLK_FIXED("periph", "xtal", 40000000)
  69 @@ -371,6 +367,12 @@ static inline struct mtmips_clk *to_mtmi
  70         return container_of(hw, struct mtmips_clk, hw);
  71  }
  72
  73 +static unsigned long rt2880_xtal_recalc_rate(struct clk_hw *hw,
  74 +                                            unsigned long parent_rate)
  75 +{
  76 +       return 40000000;
  77 +}
  78 +
  79  static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
  80                                              unsigned long parent_rate)
  81  {
  82 @@ -682,10 +684,12 @@ static unsigned long mt76x8_cpu_recalc_r
  83  }
  84
  85  static struct mtmips_clk rt2880_clks_base[] = {
  86 +       { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
  87         { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
  88  };
  89
  90  static struct mtmips_clk rt305x_clks_base[] = {
  91 +       { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
  92         { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
  93  };
  94
  95 @@ -695,6 +699,7 @@ static struct mtmips_clk rt3352_clks_bas
  96  };
  97
  98  static struct mtmips_clk rt3883_clks_base[] = {
  99 +       { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
 100         { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
 101         { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
 102  };
 103 @@ -751,8 +756,8 @@ err_clk_unreg:
 104  static const struct mtmips_clk_data rt2880_clk_data = {
 105         .clk_base = rt2880_clks_base,
 106         .num_clk_base = ARRAY_SIZE(rt2880_clks_base),
 107 -       .clk_fixed = rt305x_fixed_clocks,
 108 -       .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
 109 +       .clk_fixed = NULL,
 110 +       .num_clk_fixed = 0,
 111         .clk_factor = rt2880_factor_clocks,
 112         .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
 113         .clk_periph = rt2880_pherip_clks,
 114 @@ -762,8 +767,8 @@ static const struct mtmips_clk_data rt28
 115  static const struct mtmips_clk_data rt305x_clk_data = {
 116         .clk_base = rt305x_clks_base,
 117         .num_clk_base = ARRAY_SIZE(rt305x_clks_base),
 118 -       .clk_fixed = rt305x_fixed_clocks,
 119 -       .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
 120 +       .clk_fixed = NULL,
 121 +       .num_clk_fixed = 0,
 122         .clk_factor = rt305x_factor_clocks,
 123         .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
 124         .clk_periph = rt305x_pherip_clks,