3238a628274f5658522e27ed641f71963a4584dd
[openwrt/staging/ansuel.git] /
1 From fd051511cd5e7e38315adfe728b1481cbe480331 Mon Sep 17 00:00:00 2001
2 From: Jonathan Bell <jonathan@raspberrypi.com>
3 Date: Tue, 4 Jun 2024 09:51:17 +0100
4 Subject: [PATCH 1112/1135] mmc: sdhci-brcmstb: add hs400_downgrade callback
5 for bcm2712
6
7 The attached PHY performs parameter validation, so the switch from HS200
8 to HS (before selecting HS400/HS400es) with a 200MHz clock fails to
9 update pad timings and results in CRC errors from the card.
10
11 Underclocking the interface is safe, so do that in the downgrade callback.
12
13 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
14 ---
15 drivers/mmc/host/sdhci-brcmstb.c | 16 ++++++++++++++++
16 1 file changed, 16 insertions(+)
17
18 --- a/drivers/mmc/host/sdhci-brcmstb.c
19 +++ b/drivers/mmc/host/sdhci-brcmstb.c
20 @@ -197,6 +197,20 @@ static void sdhci_brcmstb_set_uhs_signal
21 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
22 }
23
24 +static void sdhci_bcm2712_hs400_downgrade(struct mmc_host *mmc)
25 +{
26 + struct sdhci_host *host = mmc_priv(mmc);
27 + /*
28 + * The eMMC PHY and its internal controller parses and validates
29 + * the uhs_mode, divisor, pin_sel, and sampling clock select
30 + * output from the SD controller. It will refuse to update its
31 + * config if HS timings are selected while the clock is >52MHz.
32 + * so bump the clock down now before card/controller setup is
33 + * performed.
34 + */
35 + sdhci_bcm2712_set_clock(host, 52000000);
36 +}
37 +
38 static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host)
39 {
40 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
41 @@ -215,6 +229,8 @@ static void sdhci_brcmstb_cfginit_2712(s
42 reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE;
43 reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE;
44 writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);
45 +
46 + host->mmc_host_ops.hs400_downgrade = sdhci_bcm2712_hs400_downgrade;
47 }
48
49 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||