1 From bae75b5a56bc2c8768541b4b61edb28609486357 Mon Sep 17 00:00:00 2001
2 From: Robin Gong <yibin.gong@nxp.com>
3 Date: Tue, 4 Jul 2017 14:45:25 +0800
4 Subject: [PATCH] MLK-15330-1: dma: fsl-edma-v3: combine two cells into one
6 For dual fifo case, fsl-edma-v3 need add another cell. It's not friendly
7 for user and it's possible other cells maybe added to other use cases,
8 so combine two cells into one now, and for some special use cases such as
9 dual fifo property can directly be passed by one bit of cell3 rather than
12 Signed-off-by: Robin Gong <yibin.gong@nxp.com>
13 (cherry picked from commit 3ecd1b3382e2c746728842fb2c084fbb030eb5de)
15 Documentation/devicetree/bindings/dma/fsl-edma-v3.txt | 13 +++++++------
16 drivers/dma/fsl-edma-v3.c | 9 ++++++---
17 2 files changed, 13 insertions(+), 9 deletions(-)
19 --- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
20 +++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
21 @@ -14,12 +14,13 @@ Required properties:
22 - interrupts : A list of interrupt-specifiers, each channel has one interrupt.
23 - interrupt-names : Should contain:
24 "edma-chan12-tx" - the channel12 transmission interrupt
25 -- #dma-cells : Must be <4>.
26 +- #dma-cells : Must be <3>.
27 The 1st cell specifies the channel ID.
28 The 2nd cell specifies the channel priority.
29 - The 3rd cell specifies the channel type like for transmit or receive:
30 + The 3rd cell specifies the channel attributes which include below:
31 + BIT(0): transmit or receive:
32 0: transmit, 1: receive.
33 - The 4th cell specifies the local access or remote access:
34 + BIT(1): local or remote access:
36 See the SoC's reference manual for all the supported request sources.
37 - dma-channels : Number of channels supported by the controller
38 @@ -31,7 +32,7 @@ edma0: dma-controller@40018000 {
39 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
40 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
41 <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
45 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
47 @@ -60,7 +61,7 @@ lpuart1: serial@5a070000 {
48 assigned-clock-rates = <80000000>;
49 power-domains = <&pd_dma_lpuart1>;
50 dma-names = "tx","rx";
51 - dmas = <&edma0 15 0 0 0>,
53 + dmas = <&edma0 15 0 0>,
57 --- a/drivers/dma/fsl-edma-v3.c
58 +++ b/drivers/dma/fsl-edma-v3.c
60 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \
61 BIT(DMA_SLAVE_BUSWIDTH_16_BYTES))
63 +#define ARGS_RX BIT(0)
64 +#define ARGS_REMOTE BIT(1)
66 struct fsl_edma3_hw_tcd {
69 @@ -696,7 +699,7 @@ static struct dma_chan *fsl_edma3_xlate(
70 struct dma_chan *chan, *_chan;
71 struct fsl_edma3_chan *fsl_chan;
73 - if (dma_spec->args_count != 4)
74 + if (dma_spec->args_count != 3)
77 mutex_lock(&fsl_edma3->fsl_edma3_mutex);
78 @@ -710,8 +713,8 @@ static struct dma_chan *fsl_edma3_xlate(
79 chan = dma_get_slave_channel(chan);
80 chan->device->privatecnt++;
81 fsl_chan->priority = dma_spec->args[1];
82 - fsl_chan->is_rxchan = dma_spec->args[2];
83 - fsl_chan->is_remote = dma_spec->args[3];
84 + fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
85 + fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
86 mutex_unlock(&fsl_edma3->fsl_edma3_mutex);