1 From f7704275957852cd4c4632d6da126979ef24b83a Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Tue, 2 Mar 2021 16:58:01 +0800
4 Subject: [PATCH 36/71] drivers: mtd: add support for MediaTek SPI-NAND flash
7 Add mtd driver for MediaTek SPI-NAND flash controller
9 This driver is written from scratch, and uses standard mtd framework, not
10 the nand framework which only applies for raw parallel nand flashes so that
11 this driver can have a smaller size in binary.
13 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
15 drivers/mtd/Kconfig | 2 +
16 drivers/mtd/Makefile | 2 +
17 drivers/mtd/mtk-snand/Kconfig | 21 +
18 drivers/mtd/mtk-snand/Makefile | 11 +
19 drivers/mtd/mtk-snand/mtk-snand-def.h | 271 ++++
20 drivers/mtd/mtk-snand/mtk-snand-ecc.c | 395 +++++
21 drivers/mtd/mtk-snand/mtk-snand-ids.c | 511 +++++++
22 drivers/mtd/mtk-snand/mtk-snand-mtd.c | 535 +++++++
23 drivers/mtd/mtk-snand/mtk-snand-os.c | 39 +
24 drivers/mtd/mtk-snand/mtk-snand-os.h | 120 ++
25 drivers/mtd/mtk-snand/mtk-snand.c | 1933 +++++++++++++++++++++++++
26 drivers/mtd/mtk-snand/mtk-snand.h | 77 +
27 12 files changed, 3917 insertions(+)
28 create mode 100644 drivers/mtd/mtk-snand/Kconfig
29 create mode 100644 drivers/mtd/mtk-snand/Makefile
30 create mode 100644 drivers/mtd/mtk-snand/mtk-snand-def.h
31 create mode 100644 drivers/mtd/mtk-snand/mtk-snand-ecc.c
32 create mode 100644 drivers/mtd/mtk-snand/mtk-snand-ids.c
33 create mode 100644 drivers/mtd/mtk-snand/mtk-snand-mtd.c
34 create mode 100644 drivers/mtd/mtk-snand/mtk-snand-os.c
35 create mode 100644 drivers/mtd/mtk-snand/mtk-snand-os.h
36 create mode 100644 drivers/mtd/mtk-snand/mtk-snand.c
37 create mode 100644 drivers/mtd/mtk-snand/mtk-snand.h
39 --- a/drivers/mtd/Kconfig
40 +++ b/drivers/mtd/Kconfig
41 @@ -238,6 +238,8 @@ config SYS_MAX_FLASH_BANKS_DETECT
42 to reduce the effective number of flash bank, between 0 and
43 CONFIG_SYS_MAX_FLASH_BANKS
45 +source "drivers/mtd/mtk-snand/Kconfig"
47 source "drivers/mtd/nand/Kconfig"
49 config SYS_NAND_MAX_OOBFREE
50 --- a/drivers/mtd/Makefile
51 +++ b/drivers/mtd/Makefile
52 @@ -39,3 +39,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR
53 obj-$(CONFIG_SPL_UBI) += ubispl/
57 +obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/
59 +++ b/drivers/mtd/mtk-snand/Kconfig
62 +# Copyright (C) 2020 MediaTek Inc. All rights reserved.
63 +# Author: Weijie Gao <weijie.gao@mediatek.com>
65 +# SPDX-License-Identifier: GPL-2.0
69 + tristate "MediaTek SPI NAND flash controller driver"
70 + depends on !MTD_SPI_NAND
72 + This option enables access to SPI-NAND flashes through the
73 + MediaTek SPI NAND Flash Controller
75 +config MTK_SPI_NAND_MTD
76 + tristate "MTD support for MediaTek SPI NAND flash controller"
78 + depends on MTK_SPI_NAND
80 + This option enables access to SPI-NAND flashes through the
81 + MTD interface of MediaTek SPI NAND Flash Controller
83 +++ b/drivers/mtd/mtk-snand/Makefile
86 +# Copyright (C) 2020 MediaTek Inc. All rights reserved.
87 +# Author: Weijie Gao <weijie.gao@mediatek.com>
89 +# SPDX-License-Identifier: GPL-2.0
92 +obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o
93 +obj-$(CONFIG_MTK_SPI_NAND_MTD) += mtk-snand-mtd.o
95 +ccflags-y += -DPRIVATE_MTK_SNAND_HEADER
97 +++ b/drivers/mtd/mtk-snand/mtk-snand-def.h
99 +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
101 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
103 + * Author: Weijie Gao <weijie.gao@mediatek.com>
106 +#ifndef _MTK_SNAND_DEF_H_
107 +#define _MTK_SNAND_DEF_H_
109 +#include "mtk-snand-os.h"
111 +#ifdef PRIVATE_MTK_SNAND_HEADER
112 +#include "mtk-snand.h"
114 +#include <mtk-snand.h>
117 +struct mtk_snand_plat_dev;
119 +enum snand_flash_io {
129 +#define SPI_IO_1_1_1 BIT(SNAND_IO_1_1_1)
130 +#define SPI_IO_1_1_2 BIT(SNAND_IO_1_1_2)
131 +#define SPI_IO_1_2_2 BIT(SNAND_IO_1_2_2)
132 +#define SPI_IO_1_1_4 BIT(SNAND_IO_1_1_4)
133 +#define SPI_IO_1_4_4 BIT(SNAND_IO_1_4_4)
135 +struct snand_opcode {
140 +struct snand_io_cap {
142 + struct snand_opcode opcodes[__SNAND_IO_MAX];
145 +#define SNAND_OP(_io, _opcode, _dummy) [_io] = { .opcode = (_opcode), \
146 + .dummy = (_dummy) }
148 +#define SNAND_IO_CAP(_name, _caps, ...) \
149 + struct snand_io_cap _name = { .caps = (_caps), \
150 + .opcodes = { __VA_ARGS__ } }
152 +#define SNAND_MAX_ID_LEN 4
154 +enum snand_id_type {
156 + SNAND_ID_ADDR = SNAND_ID_DYMMY,
159 + __SNAND_ID_TYPE_MAX
163 + uint8_t type; /* enum snand_id_type */
165 + uint8_t id[SNAND_MAX_ID_LEN];
168 +#define SNAND_ID(_type, ...) \
169 + { .type = (_type), .id = { __VA_ARGS__ }, \
170 + .len = sizeof((uint8_t[]) { __VA_ARGS__ }) }
172 +struct snand_mem_org {
174 + uint16_t sparesize;
175 + uint16_t pages_per_block;
176 + uint16_t blocks_per_die;
177 + uint16_t planes_per_die;
181 +#define SNAND_MEMORG(_ps, _ss, _ppb, _bpd, _ppd, _nd) \
182 + { .pagesize = (_ps), .sparesize = (_ss), .pages_per_block = (_ppb), \
183 + .blocks_per_die = (_bpd), .planes_per_die = (_ppd), .ndies = (_nd) }
185 +typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx);
187 +struct snand_flash_info {
189 + struct snand_id id;
190 + const struct snand_mem_org memorg;
191 + const struct snand_io_cap *cap_rd;
192 + const struct snand_io_cap *cap_pl;
193 + snand_select_die_t select_die;
196 +#define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \
197 + { .model = (_model), .id = _id, .memorg = _memorg, \
198 + .cap_rd = (_cap_rd), .cap_pl = (_cap_pl), __VA_ARGS__ }
200 +const struct snand_flash_info *snand_flash_id_lookup(enum snand_id_type type,
201 + const uint8_t *id);
203 +struct mtk_snand_soc_data {
204 + uint16_t sector_size;
205 + uint16_t max_sectors;
207 + uint16_t fdm_ecc_size;
208 + uint16_t fifo_size;
211 + bool empty_page_check;
212 + uint32_t mastersta_mask;
214 + const uint8_t *spare_sizes;
215 + uint32_t num_spare_size;
217 + uint16_t latch_lat;
218 + uint16_t sample_delay;
225 +struct mtk_ecc_soc_data {
226 + const uint8_t *ecc_caps;
227 + uint32_t num_ecc_cap;
228 + const uint32_t *regs;
229 + uint16_t mode_shift;
230 + uint8_t errnum_bits;
231 + uint8_t errnum_shift;
235 + struct mtk_snand_plat_dev *pdev;
237 + void __iomem *nfi_base;
238 + void __iomem *ecc_base;
240 + enum mtk_snand_soc soc;
241 + const struct mtk_snand_soc_data *nfi_soc;
242 + const struct mtk_ecc_soc_data *ecc_soc;
243 + bool snfi_quad_spi;
249 + uint32_t erasesize;
250 + uint32_t writesize;
254 + snand_select_die_t select_die;
256 + uint8_t opcode_rfc;
262 + uint32_t writesize_mask;
263 + uint32_t writesize_shift;
264 + uint32_t erasesize_mask;
265 + uint32_t erasesize_shift;
267 + uint32_t die_shift;
269 + uint32_t spare_per_sector;
270 + uint32_t raw_sector_size;
271 + uint32_t ecc_strength;
272 + uint32_t ecc_steps;
273 + uint32_t ecc_bytes;
274 + uint32_t ecc_parity_bits;
276 + uint8_t *page_cache; /* Used by read/write page */
277 + uint8_t *buf_cache; /* Used by block bad/markbad & auto_oob */
278 + int *sect_bf; /* Used by ECC correction */
281 +enum mtk_snand_log_category {
287 + __SNAND_LOG_CAT_MAX
290 +int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes,
291 + uint32_t msg_size);
292 +int mtk_snand_ecc_encoder_start(struct mtk_snand *snf);
293 +void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf);
294 +int mtk_snand_ecc_decoder_start(struct mtk_snand *snf);
295 +void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf);
296 +int mtk_ecc_wait_decoder_done(struct mtk_snand *snf);
297 +int mtk_ecc_check_decode_error(struct mtk_snand *snf);
298 +int mtk_ecc_fixup_empty_sector(struct mtk_snand *snf, uint32_t sect);
300 +int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen,
301 + uint8_t *in, uint32_t inlen);
302 +int mtk_snand_set_feature(struct mtk_snand *snf, uint32_t addr, uint32_t val);
304 +int mtk_snand_log(struct mtk_snand_plat_dev *pdev,
305 + enum mtk_snand_log_category cat, const char *fmt, ...);
307 +#define snand_log_nfi(pdev, fmt, ...) \
308 + mtk_snand_log(pdev, SNAND_LOG_NFI, fmt, ##__VA_ARGS__)
310 +#define snand_log_snfi(pdev, fmt, ...) \
311 + mtk_snand_log(pdev, SNAND_LOG_SNFI, fmt, ##__VA_ARGS__)
313 +#define snand_log_ecc(pdev, fmt, ...) \
314 + mtk_snand_log(pdev, SNAND_LOG_ECC, fmt, ##__VA_ARGS__)
316 +#define snand_log_chip(pdev, fmt, ...) \
317 + mtk_snand_log(pdev, SNAND_LOG_CHIP, fmt, ##__VA_ARGS__)
320 +static inline int mtk_snand_ffs64(uint64_t x)
325 + if (!(x & 0xffffffff))
326 + return ffs((uint32_t)(x >> 32)) + 32;
328 + return ffs((uint32_t)(x & 0xffffffff));
331 +/* NFI dummy commands */
332 +#define NFI_CMD_DUMMY_READ 0x00
333 +#define NFI_CMD_DUMMY_WRITE 0x80
335 +/* SPI-NAND opcodes */
336 +#define SNAND_CMD_RESET 0xff
337 +#define SNAND_CMD_BLOCK_ERASE 0xd8
338 +#define SNAND_CMD_READ_FROM_CACHE_QUAD 0xeb
339 +#define SNAND_CMD_WINBOND_SELECT_DIE 0xc2
340 +#define SNAND_CMD_READ_FROM_CACHE_DUAL 0xbb
341 +#define SNAND_CMD_READID 0x9f
342 +#define SNAND_CMD_READ_FROM_CACHE_X4 0x6b
343 +#define SNAND_CMD_READ_FROM_CACHE_X2 0x3b
344 +#define SNAND_CMD_PROGRAM_LOAD_X4 0x32
345 +#define SNAND_CMD_SET_FEATURE 0x1f
346 +#define SNAND_CMD_READ_TO_CACHE 0x13
347 +#define SNAND_CMD_PROGRAM_EXECUTE 0x10
348 +#define SNAND_CMD_GET_FEATURE 0x0f
349 +#define SNAND_CMD_READ_FROM_CACHE 0x0b
350 +#define SNAND_CMD_WRITE_ENABLE 0x06
351 +#define SNAND_CMD_PROGRAM_LOAD 0x02
353 +/* SPI-NAND feature addresses */
354 +#define SNAND_FEATURE_MICRON_DIE_ADDR 0xd0
355 +#define SNAND_MICRON_DIE_SEL_1 BIT(6)
357 +#define SNAND_FEATURE_STATUS_ADDR 0xc0
358 +#define SNAND_STATUS_OIP BIT(0)
359 +#define SNAND_STATUS_WEL BIT(1)
360 +#define SNAND_STATUS_ERASE_FAIL BIT(2)
361 +#define SNAND_STATUS_PROGRAM_FAIL BIT(3)
363 +#define SNAND_FEATURE_CONFIG_ADDR 0xb0
364 +#define SNAND_FEATURE_QUAD_ENABLE BIT(0)
365 +#define SNAND_FEATURE_ECC_EN BIT(4)
367 +#define SNAND_FEATURE_PROTECT_ADDR 0xa0
369 +#endif /* _MTK_SNAND_DEF_H_ */
371 +++ b/drivers/mtd/mtk-snand/mtk-snand-ecc.c
373 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
375 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
377 + * Author: Weijie Gao <weijie.gao@mediatek.com>
380 +#include "mtk-snand-def.h"
383 +#define ECC_ENCCON 0x000
384 +#define ENC_EN BIT(0)
386 +#define ECC_ENCCNFG 0x004
388 +#define ENC_BURST_EN BIT(8)
389 +#define ENC_TNUM_S 0
391 +#define ECC_ENCIDLE 0x00c
392 +#define ENC_IDLE BIT(0)
394 +#define ECC_DECCON 0x100
395 +#define DEC_EN BIT(0)
397 +#define ECC_DECCNFG 0x104
398 +#define DEC_EMPTY_EN BIT(31)
400 +#define DEC_CON_S 12
401 +#define DEC_CON_CORRECT 3
402 +#define DEC_BURST_EN BIT(8)
403 +#define DEC_TNUM_S 0
405 +#define ECC_DECIDLE 0x10c
406 +#define DEC_IDLE BIT(0)
408 +#define ECC_DECENUM0 0x114
409 +#define ECC_DECENUM(n) (ECC_DECENUM0 + (n) * 4)
411 +/* ECC_ENCIDLE & ECC_DECIDLE */
412 +#define ECC_IDLE BIT(0)
414 +/* ENC_MODE & DEC_MODE */
415 +#define ECC_MODE_NFI 1
417 +#define ECC_TIMEOUT 500000
419 +static const uint8_t mt7622_ecc_caps[] = { 4, 6, 8, 10, 12 };
421 +static const uint8_t mt7986_ecc_caps[] = {
422 + 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
425 +static const uint32_t mt7622_ecc_regs[] = {
426 + [ECC_DECDONE] = 0x11c,
429 +static const uint32_t mt7986_ecc_regs[] = {
430 + [ECC_DECDONE] = 0x124,
433 +static const struct mtk_ecc_soc_data mtk_ecc_socs[__SNAND_SOC_MAX] = {
434 + [SNAND_SOC_MT7622] = {
435 + .ecc_caps = mt7622_ecc_caps,
436 + .num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps),
437 + .regs = mt7622_ecc_regs,
442 + [SNAND_SOC_MT7629] = {
443 + .ecc_caps = mt7622_ecc_caps,
444 + .num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps),
445 + .regs = mt7622_ecc_regs,
450 + [SNAND_SOC_MT7986] = {
451 + .ecc_caps = mt7986_ecc_caps,
452 + .num_ecc_cap = ARRAY_SIZE(mt7986_ecc_caps),
453 + .regs = mt7986_ecc_regs,
460 +static inline uint32_t ecc_read32(struct mtk_snand *snf, uint32_t reg)
462 + return readl(snf->ecc_base + reg);
465 +static inline void ecc_write32(struct mtk_snand *snf, uint32_t reg,
468 + writel(val, snf->ecc_base + reg);
471 +static inline void ecc_write16(struct mtk_snand *snf, uint32_t reg,
474 + writew(val, snf->ecc_base + reg);
477 +static int mtk_ecc_poll(struct mtk_snand *snf, uint32_t reg, uint32_t bits)
481 + return read16_poll_timeout(snf->ecc_base + reg, val, (val & bits), 0,
485 +static int mtk_ecc_wait_idle(struct mtk_snand *snf, uint32_t reg)
489 + ret = mtk_ecc_poll(snf, reg, ECC_IDLE);
491 + snand_log_ecc(snf->pdev, "ECC engine is busy\n");
498 +int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes,
501 + uint32_t i, val, ecc_msg_bits, ecc_strength;
504 + snf->ecc_soc = &mtk_ecc_socs[snf->soc];
506 + snf->ecc_parity_bits = fls(1 + 8 * msg_size);
507 + ecc_strength = max_ecc_bytes * 8 / snf->ecc_parity_bits;
509 + for (i = snf->ecc_soc->num_ecc_cap - 1; i >= 0; i--) {
510 + if (snf->ecc_soc->ecc_caps[i] <= ecc_strength)
514 + if (unlikely(i < 0)) {
515 + snand_log_ecc(snf->pdev, "Page size %u+%u is not supported\n",
516 + snf->writesize, snf->oobsize);
520 + snf->ecc_strength = snf->ecc_soc->ecc_caps[i];
521 + snf->ecc_bytes = DIV_ROUND_UP(snf->ecc_strength * snf->ecc_parity_bits,
524 + /* Encoder config */
525 + ecc_write16(snf, ECC_ENCCON, 0);
526 + ret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE);
530 + ecc_msg_bits = msg_size * 8;
531 + val = (ecc_msg_bits << ENC_MS_S) |
532 + (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i;
533 + ecc_write32(snf, ECC_ENCCNFG, val);
535 + /* Decoder config */
536 + ecc_write16(snf, ECC_DECCON, 0);
537 + ret = mtk_ecc_wait_idle(snf, ECC_DECIDLE);
541 + ecc_msg_bits += snf->ecc_strength * snf->ecc_parity_bits;
542 + val = DEC_EMPTY_EN | (ecc_msg_bits << DEC_CS_S) |
543 + (DEC_CON_CORRECT << DEC_CON_S) |
544 + (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i;
545 + ecc_write32(snf, ECC_DECCNFG, val);
550 +int mtk_snand_ecc_encoder_start(struct mtk_snand *snf)
554 + ret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE);
556 + ecc_write16(snf, ECC_ENCCON, 0);
557 + mtk_ecc_wait_idle(snf, ECC_ENCIDLE);
560 + ecc_write16(snf, ECC_ENCCON, ENC_EN);
565 +void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf)
567 + mtk_ecc_wait_idle(snf, ECC_ENCIDLE);
568 + ecc_write16(snf, ECC_ENCCON, 0);
571 +int mtk_snand_ecc_decoder_start(struct mtk_snand *snf)
575 + ret = mtk_ecc_wait_idle(snf, ECC_DECIDLE);
577 + ecc_write16(snf, ECC_DECCON, 0);
578 + mtk_ecc_wait_idle(snf, ECC_DECIDLE);
581 + ecc_write16(snf, ECC_DECCON, DEC_EN);
586 +void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf)
588 + mtk_ecc_wait_idle(snf, ECC_DECIDLE);
589 + ecc_write16(snf, ECC_DECCON, 0);
592 +int mtk_ecc_wait_decoder_done(struct mtk_snand *snf)
594 + uint16_t val, step_mask = (1 << snf->ecc_steps) - 1;
595 + uint32_t reg = snf->ecc_soc->regs[ECC_DECDONE];
598 + ret = read16_poll_timeout(snf->ecc_base + reg, val,
599 + (val & step_mask) == step_mask, 0,
602 + snand_log_ecc(snf->pdev, "ECC decoder is busy\n");
607 +int mtk_ecc_check_decode_error(struct mtk_snand *snf)
609 + uint32_t i, regi, fi, errnum;
610 + uint32_t errnum_shift = snf->ecc_soc->errnum_shift;
611 + uint32_t errnum_mask = (1 << snf->ecc_soc->errnum_bits) - 1;
614 + for (i = 0; i < snf->ecc_steps; i++) {
618 + errnum = ecc_read32(snf, ECC_DECENUM(regi));
619 + errnum = (errnum >> (fi * errnum_shift)) & errnum_mask;
621 + if (errnum <= snf->ecc_strength) {
622 + snf->sect_bf[i] = errnum;
624 + snf->sect_bf[i] = -1;
632 +static int mtk_ecc_check_buf_bitflips(struct mtk_snand *snf, const void *buf,
633 + size_t len, uint32_t bitflips)
635 + const uint8_t *buf8 = buf;
636 + const uint32_t *buf32;
637 + uint32_t d, weight;
639 + while (len && ((uintptr_t)buf8) % sizeof(uint32_t)) {
640 + weight = hweight8(*buf8);
641 + bitflips += BITS_PER_BYTE - weight;
645 + if (bitflips > snf->ecc_strength)
649 + buf32 = (const uint32_t *)buf8;
650 + while (len >= sizeof(uint32_t)) {
654 + weight = hweight32(d);
655 + bitflips += sizeof(uint32_t) * BITS_PER_BYTE - weight;
659 + len -= sizeof(uint32_t);
661 + if (bitflips > snf->ecc_strength)
665 + buf8 = (const uint8_t *)buf32;
667 + weight = hweight8(*buf8);
668 + bitflips += BITS_PER_BYTE - weight;
672 + if (bitflips > snf->ecc_strength)
679 +static int mtk_ecc_check_parity_bitflips(struct mtk_snand *snf, const void *buf,
680 + uint32_t bits, uint32_t bitflips)
689 + rc = mtk_ecc_check_buf_bitflips(snf, buf, len, bitflips);
690 + if (!bits || rc < 0)
695 + /* We want a precise count of bits */
696 + b = ((const uint8_t *)buf)[len];
697 + for (i = 0; i < bits; i++) {
702 + if (bitflips > snf->ecc_strength)
708 +static void mtk_ecc_reset_parity(void *buf, uint32_t bits)
715 + memset(buf, 0xff, len);
717 + /* Only reset bits protected by ECC to 1 */
719 + ((uint8_t *)buf)[len] |= GENMASK(bits - 1, 0);
722 +int mtk_ecc_fixup_empty_sector(struct mtk_snand *snf, uint32_t sect)
724 + uint32_t ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size;
725 + uint8_t *oob = snf->page_cache + snf->writesize;
726 + uint8_t *data_ptr, *fdm_ptr, *ecc_ptr;
727 + int bitflips = 0, ecc_bits, parity_bits;
729 + parity_bits = fls(snf->nfi_soc->sector_size * 8);
730 + ecc_bits = snf->ecc_strength * parity_bits;
732 + data_ptr = snf->page_cache + sect * snf->nfi_soc->sector_size;
733 + fdm_ptr = oob + sect * snf->nfi_soc->fdm_size;
734 + ecc_ptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size +
738 + * Check whether DATA + FDM + ECC of a sector contains correctable
741 + bitflips = mtk_ecc_check_buf_bitflips(snf, data_ptr,
742 + snf->nfi_soc->sector_size,
747 + bitflips = mtk_ecc_check_buf_bitflips(snf, fdm_ptr,
748 + snf->nfi_soc->fdm_ecc_size,
753 + bitflips = mtk_ecc_check_parity_bitflips(snf, ecc_ptr, ecc_bits,
761 + /* Reset the data of this sector to 0xff */
762 + memset(data_ptr, 0xff, snf->nfi_soc->sector_size);
763 + memset(fdm_ptr, 0xff, snf->nfi_soc->fdm_ecc_size);
764 + mtk_ecc_reset_parity(ecc_ptr, ecc_bits);
769 +++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c
771 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
773 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
775 + * Author: Weijie Gao <weijie.gao@mediatek.com>
778 +#include "mtk-snand-def.h"
780 +static int mtk_snand_winbond_select_die(struct mtk_snand *snf, uint32_t dieidx);
781 +static int mtk_snand_micron_select_die(struct mtk_snand *snf, uint32_t dieidx);
783 +#define SNAND_MEMORG_512M_2K_64 SNAND_MEMORG(2048, 64, 64, 512, 1, 1)
784 +#define SNAND_MEMORG_1G_2K_64 SNAND_MEMORG(2048, 64, 64, 1024, 1, 1)
785 +#define SNAND_MEMORG_2G_2K_64 SNAND_MEMORG(2048, 64, 64, 2048, 1, 1)
786 +#define SNAND_MEMORG_2G_2K_120 SNAND_MEMORG(2048, 120, 64, 2048, 1, 1)
787 +#define SNAND_MEMORG_4G_2K_64 SNAND_MEMORG(2048, 64, 64, 4096, 1, 1)
788 +#define SNAND_MEMORG_1G_2K_120 SNAND_MEMORG(2048, 120, 64, 1024, 1, 1)
789 +#define SNAND_MEMORG_1G_2K_128 SNAND_MEMORG(2048, 128, 64, 1024, 1, 1)
790 +#define SNAND_MEMORG_2G_2K_128 SNAND_MEMORG(2048, 128, 64, 2048, 1, 1)
791 +#define SNAND_MEMORG_4G_2K_128 SNAND_MEMORG(2048, 128, 64, 4096, 1, 1)
792 +#define SNAND_MEMORG_4G_4K_240 SNAND_MEMORG(4096, 240, 64, 2048, 1, 1)
793 +#define SNAND_MEMORG_4G_4K_256 SNAND_MEMORG(4096, 256, 64, 2048, 1, 1)
794 +#define SNAND_MEMORG_8G_4K_256 SNAND_MEMORG(4096, 256, 64, 4096, 1, 1)
795 +#define SNAND_MEMORG_2G_2K_64_2P SNAND_MEMORG(2048, 64, 64, 2048, 2, 1)
796 +#define SNAND_MEMORG_2G_2K_64_2D SNAND_MEMORG(2048, 64, 64, 1024, 1, 2)
797 +#define SNAND_MEMORG_2G_2K_128_2P SNAND_MEMORG(2048, 128, 64, 2048, 2, 1)
798 +#define SNAND_MEMORG_4G_2K_64_2P SNAND_MEMORG(2048, 64, 64, 4096, 2, 1)
799 +#define SNAND_MEMORG_4G_2K_128_2P_2D SNAND_MEMORG(2048, 128, 64, 2048, 2, 2)
800 +#define SNAND_MEMORG_8G_4K_256_2D SNAND_MEMORG(4096, 256, 64, 2048, 1, 2)
802 +static const SNAND_IO_CAP(snand_cap_read_from_cache_quad,
803 + SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 |
805 + SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
806 + SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),
807 + SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4),
808 + SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8),
809 + SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 4));
811 +static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_q2d,
812 + SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 |
814 + SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
815 + SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),
816 + SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4),
817 + SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8),
818 + SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 2));
820 +static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_a8d,
821 + SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 |
823 + SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
824 + SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),
825 + SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 8),
826 + SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8),
827 + SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 8));
829 +static const SNAND_IO_CAP(snand_cap_read_from_cache_x4,
830 + SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_1_4,
831 + SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
832 + SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),
833 + SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8));
835 +static const SNAND_IO_CAP(snand_cap_read_from_cache_x4_only,
836 + SPI_IO_1_1_1 | SPI_IO_1_1_4,
837 + SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),
838 + SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8));
840 +static const SNAND_IO_CAP(snand_cap_program_load_x1,
842 + SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0));
844 +static const SNAND_IO_CAP(snand_cap_program_load_x4,
845 + SPI_IO_1_1_1 | SPI_IO_1_1_4,
846 + SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0),
847 + SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_PROGRAM_LOAD_X4, 0));
849 +static const struct snand_flash_info snand_flash_ids[] = {
850 + SNAND_INFO("W25N512GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x20),
851 + SNAND_MEMORG_512M_2K_64,
852 + &snand_cap_read_from_cache_quad,
853 + &snand_cap_program_load_x4),
854 + SNAND_INFO("W25N01GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x21),
855 + SNAND_MEMORG_1G_2K_64,
856 + &snand_cap_read_from_cache_quad,
857 + &snand_cap_program_load_x4),
858 + SNAND_INFO("W25M02GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xab, 0x21),
859 + SNAND_MEMORG_2G_2K_64_2D,
860 + &snand_cap_read_from_cache_quad,
861 + &snand_cap_program_load_x4,
862 + mtk_snand_winbond_select_die),
863 + SNAND_INFO("W25N02KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22),
864 + SNAND_MEMORG_2G_2K_128,
865 + &snand_cap_read_from_cache_quad,
866 + &snand_cap_program_load_x4),
868 + SNAND_INFO("GD5F1GQ4UAWxx", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x10),
869 + SNAND_MEMORG_1G_2K_64,
870 + &snand_cap_read_from_cache_quad_q2d,
871 + &snand_cap_program_load_x4),
872 + SNAND_INFO("GD5F1GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd1),
873 + SNAND_MEMORG_1G_2K_128,
874 + &snand_cap_read_from_cache_quad_q2d,
875 + &snand_cap_program_load_x4),
876 + SNAND_INFO("GD5F1GQ4UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd9),
877 + SNAND_MEMORG_1G_2K_64,
878 + &snand_cap_read_from_cache_quad_q2d,
879 + &snand_cap_program_load_x4),
880 + SNAND_INFO("GD5F1GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf1),
881 + SNAND_MEMORG_1G_2K_64,
882 + &snand_cap_read_from_cache_quad_q2d,
883 + &snand_cap_program_load_x4),
884 + SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
885 + SNAND_MEMORG_2G_2K_128,
886 + &snand_cap_read_from_cache_quad_q2d,
887 + &snand_cap_program_load_x4),
888 + SNAND_INFO("GD5F2GQ5UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x32),
889 + SNAND_MEMORG_2G_2K_64,
890 + &snand_cap_read_from_cache_quad_a8d,
891 + &snand_cap_program_load_x4),
892 + SNAND_INFO("GD5F2GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf2),
893 + SNAND_MEMORG_2G_2K_64,
894 + &snand_cap_read_from_cache_quad_q2d,
895 + &snand_cap_program_load_x4),
896 + SNAND_INFO("GD5F4GQ4UBxIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd4),
897 + SNAND_MEMORG_4G_4K_256,
898 + &snand_cap_read_from_cache_quad_q2d,
899 + &snand_cap_program_load_x4),
900 + SNAND_INFO("GD5F4GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf4),
901 + SNAND_MEMORG_4G_2K_64,
902 + &snand_cap_read_from_cache_quad_q2d,
903 + &snand_cap_program_load_x4),
904 + SNAND_INFO("GD5F2GQ5UExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52),
905 + SNAND_MEMORG_2G_2K_128,
906 + &snand_cap_read_from_cache_quad_q2d,
907 + &snand_cap_program_load_x4),
908 + SNAND_INFO("GD5F4GQ4UCxIG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4),
909 + SNAND_MEMORG_4G_4K_256,
910 + &snand_cap_read_from_cache_quad_q2d,
911 + &snand_cap_program_load_x4),
913 + SNAND_INFO("MX35LF1GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x12),
914 + SNAND_MEMORG_1G_2K_64,
915 + &snand_cap_read_from_cache_x4,
916 + &snand_cap_program_load_x4),
917 + SNAND_INFO("MX35LF1G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x14),
918 + SNAND_MEMORG_1G_2K_128,
919 + &snand_cap_read_from_cache_quad,
920 + &snand_cap_program_load_x4),
921 + SNAND_INFO("MX31LF1GE4BC", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x1e),
922 + SNAND_MEMORG_1G_2K_64,
923 + &snand_cap_read_from_cache_x4,
924 + &snand_cap_program_load_x4),
925 + SNAND_INFO("MX35LF2GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x22),
926 + SNAND_MEMORG_2G_2K_64,
927 + &snand_cap_read_from_cache_x4,
928 + &snand_cap_program_load_x4),
929 + SNAND_INFO("MX35LF2G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x24),
930 + SNAND_MEMORG_2G_2K_128,
931 + &snand_cap_read_from_cache_quad,
932 + &snand_cap_program_load_x4),
933 + SNAND_INFO("MX35LF2GE4AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x26),
934 + SNAND_MEMORG_2G_2K_128,
935 + &snand_cap_read_from_cache_x4,
936 + &snand_cap_program_load_x4),
937 + SNAND_INFO("MX35LF2G14AC", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x20),
938 + SNAND_MEMORG_2G_2K_64,
939 + &snand_cap_read_from_cache_x4,
940 + &snand_cap_program_load_x4),
941 + SNAND_INFO("MX35LF4G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x35),
942 + SNAND_MEMORG_4G_4K_256,
943 + &snand_cap_read_from_cache_quad,
944 + &snand_cap_program_load_x4),
945 + SNAND_INFO("MX35LF4GE4AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x37),
946 + SNAND_MEMORG_4G_4K_256,
947 + &snand_cap_read_from_cache_x4,
948 + &snand_cap_program_load_x4),
950 + SNAND_INFO("MT29F1G01AAADD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x12),
951 + SNAND_MEMORG_1G_2K_64,
952 + &snand_cap_read_from_cache_x4,
953 + &snand_cap_program_load_x1),
954 + SNAND_INFO("MT29F1G01ABAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x14),
955 + SNAND_MEMORG_1G_2K_128,
956 + &snand_cap_read_from_cache_quad,
957 + &snand_cap_program_load_x4),
958 + SNAND_INFO("MT29F2G01AAAED", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x9f),
959 + SNAND_MEMORG_2G_2K_64_2P,
960 + &snand_cap_read_from_cache_x4,
961 + &snand_cap_program_load_x1),
962 + SNAND_INFO("MT29F2G01ABAGD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x24),
963 + SNAND_MEMORG_2G_2K_128_2P,
964 + &snand_cap_read_from_cache_quad,
965 + &snand_cap_program_load_x4),
966 + SNAND_INFO("MT29F4G01AAADD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x32),
967 + SNAND_MEMORG_4G_2K_64_2P,
968 + &snand_cap_read_from_cache_x4,
969 + &snand_cap_program_load_x1),
970 + SNAND_INFO("MT29F4G01ABAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x34),
971 + SNAND_MEMORG_4G_4K_256,
972 + &snand_cap_read_from_cache_quad,
973 + &snand_cap_program_load_x4),
974 + SNAND_INFO("MT29F4G01ADAGD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x36),
975 + SNAND_MEMORG_4G_2K_128_2P_2D,
976 + &snand_cap_read_from_cache_quad,
977 + &snand_cap_program_load_x4,
978 + mtk_snand_micron_select_die),
979 + SNAND_INFO("MT29F8G01ADAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x46),
980 + SNAND_MEMORG_8G_4K_256_2D,
981 + &snand_cap_read_from_cache_quad,
982 + &snand_cap_program_load_x4,
983 + mtk_snand_micron_select_die),
985 + SNAND_INFO("TC58CVG0S3HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xc2),
986 + SNAND_MEMORG_1G_2K_128,
987 + &snand_cap_read_from_cache_x4,
988 + &snand_cap_program_load_x1),
989 + SNAND_INFO("TC58CVG1S3HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcb),
990 + SNAND_MEMORG_2G_2K_128,
991 + &snand_cap_read_from_cache_x4,
992 + &snand_cap_program_load_x1),
993 + SNAND_INFO("TC58CVG2S0HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcd),
994 + SNAND_MEMORG_4G_4K_256,
995 + &snand_cap_read_from_cache_x4,
996 + &snand_cap_program_load_x1),
997 + SNAND_INFO("TC58CVG0S3HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe2),
998 + SNAND_MEMORG_1G_2K_128,
999 + &snand_cap_read_from_cache_x4,
1000 + &snand_cap_program_load_x4),
1001 + SNAND_INFO("TC58CVG1S3HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xeb),
1002 + SNAND_MEMORG_2G_2K_128,
1003 + &snand_cap_read_from_cache_x4,
1004 + &snand_cap_program_load_x4),
1005 + SNAND_INFO("TC58CVG2S0HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xed),
1006 + SNAND_MEMORG_4G_4K_256,
1007 + &snand_cap_read_from_cache_x4,
1008 + &snand_cap_program_load_x4),
1009 + SNAND_INFO("TH58CVG3S0HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe4),
1010 + SNAND_MEMORG_8G_4K_256,
1011 + &snand_cap_read_from_cache_x4,
1012 + &snand_cap_program_load_x4),
1014 + SNAND_INFO("F50L512M41A", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x20),
1015 + SNAND_MEMORG_512M_2K_64,
1016 + &snand_cap_read_from_cache_x4,
1017 + &snand_cap_program_load_x4),
1018 + SNAND_INFO("F50L1G41A", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x21),
1019 + SNAND_MEMORG_1G_2K_64,
1020 + &snand_cap_read_from_cache_x4,
1021 + &snand_cap_program_load_x4),
1022 + SNAND_INFO("F50L1G41LB", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x01),
1023 + SNAND_MEMORG_1G_2K_64,
1024 + &snand_cap_read_from_cache_quad,
1025 + &snand_cap_program_load_x4),
1026 + SNAND_INFO("F50L2G41LB", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x0a),
1027 + SNAND_MEMORG_2G_2K_64_2D,
1028 + &snand_cap_read_from_cache_quad,
1029 + &snand_cap_program_load_x4,
1030 + mtk_snand_winbond_select_die),
1032 + SNAND_INFO("CS11G0T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x00),
1033 + SNAND_MEMORG_1G_2K_128,
1034 + &snand_cap_read_from_cache_quad_q2d,
1035 + &snand_cap_program_load_x4),
1036 + SNAND_INFO("CS11G0G0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x10),
1037 + SNAND_MEMORG_1G_2K_128,
1038 + &snand_cap_read_from_cache_quad_q2d,
1039 + &snand_cap_program_load_x4),
1040 + SNAND_INFO("CS11G0S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x20),
1041 + SNAND_MEMORG_1G_2K_64,
1042 + &snand_cap_read_from_cache_quad_q2d,
1043 + &snand_cap_program_load_x4),
1044 + SNAND_INFO("CS11G1T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x01),
1045 + SNAND_MEMORG_2G_2K_128,
1046 + &snand_cap_read_from_cache_quad_q2d,
1047 + &snand_cap_program_load_x4),
1048 + SNAND_INFO("CS11G1S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x21),
1049 + SNAND_MEMORG_2G_2K_64,
1050 + &snand_cap_read_from_cache_quad_q2d,
1051 + &snand_cap_program_load_x4),
1052 + SNAND_INFO("CS11G2T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x02),
1053 + SNAND_MEMORG_4G_2K_128,
1054 + &snand_cap_read_from_cache_quad_q2d,
1055 + &snand_cap_program_load_x4),
1056 + SNAND_INFO("CS11G2S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x22),
1057 + SNAND_MEMORG_4G_2K_64,
1058 + &snand_cap_read_from_cache_quad_q2d,
1059 + &snand_cap_program_load_x4),
1061 + SNAND_INFO("EM73B044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x01),
1062 + SNAND_MEMORG_512M_2K_64,
1063 + &snand_cap_read_from_cache_quad_q2d,
1064 + &snand_cap_program_load_x4),
1065 + SNAND_INFO("EM73C044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x11),
1066 + SNAND_MEMORG_1G_2K_120,
1067 + &snand_cap_read_from_cache_quad_q2d,
1068 + &snand_cap_program_load_x4),
1069 + SNAND_INFO("EM73C044SNF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x09),
1070 + SNAND_MEMORG_1G_2K_128,
1071 + &snand_cap_read_from_cache_quad_q2d,
1072 + &snand_cap_program_load_x4),
1073 + SNAND_INFO("EM73C044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x18),
1074 + SNAND_MEMORG_1G_2K_64,
1075 + &snand_cap_read_from_cache_quad_q2d,
1076 + &snand_cap_program_load_x4),
1077 + SNAND_INFO("EM73C044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x19),
1078 + SNAND_MEMORG(2048, 64, 128, 512, 1, 1),
1079 + &snand_cap_read_from_cache_quad_q2d,
1080 + &snand_cap_program_load_x4),
1081 + SNAND_INFO("EM73C044VCD", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1c),
1082 + SNAND_MEMORG_1G_2K_64,
1083 + &snand_cap_read_from_cache_quad_q2d,
1084 + &snand_cap_program_load_x4),
1085 + SNAND_INFO("EM73C044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d),
1086 + SNAND_MEMORG_1G_2K_64,
1087 + &snand_cap_read_from_cache_quad_q2d,
1088 + &snand_cap_program_load_x4),
1089 + SNAND_INFO("EM73D044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1e),
1090 + SNAND_MEMORG_2G_2K_64,
1091 + &snand_cap_read_from_cache_quad_q2d,
1092 + &snand_cap_program_load_x4),
1093 + SNAND_INFO("EM73C044VCC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x22),
1094 + SNAND_MEMORG_1G_2K_64,
1095 + &snand_cap_read_from_cache_quad_q2d,
1096 + &snand_cap_program_load_x4),
1097 + SNAND_INFO("EM73C044VCF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x25),
1098 + SNAND_MEMORG_1G_2K_64,
1099 + &snand_cap_read_from_cache_quad_q2d,
1100 + &snand_cap_program_load_x4),
1101 + SNAND_INFO("EM73C044SNC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x31),
1102 + SNAND_MEMORG_1G_2K_128,
1103 + &snand_cap_read_from_cache_quad_q2d,
1104 + &snand_cap_program_load_x4),
1105 + SNAND_INFO("EM73D044SNC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0a),
1106 + SNAND_MEMORG_2G_2K_120,
1107 + &snand_cap_read_from_cache_quad_q2d,
1108 + &snand_cap_program_load_x4),
1109 + SNAND_INFO("EM73D044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x12),
1110 + SNAND_MEMORG_2G_2K_128,
1111 + &snand_cap_read_from_cache_quad_q2d,
1112 + &snand_cap_program_load_x4),
1113 + SNAND_INFO("EM73D044SNF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x10),
1114 + SNAND_MEMORG_2G_2K_128,
1115 + &snand_cap_read_from_cache_quad_q2d,
1116 + &snand_cap_program_load_x4),
1117 + SNAND_INFO("EM73D044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x13),
1118 + SNAND_MEMORG_2G_2K_128,
1119 + &snand_cap_read_from_cache_quad_q2d,
1120 + &snand_cap_program_load_x4),
1121 + SNAND_INFO("EM73D044VCB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x14),
1122 + SNAND_MEMORG_2G_2K_64,
1123 + &snand_cap_read_from_cache_quad_q2d,
1124 + &snand_cap_program_load_x4),
1125 + SNAND_INFO("EM73D044VCD", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x17),
1126 + SNAND_MEMORG_2G_2K_128,
1127 + &snand_cap_read_from_cache_quad_q2d,
1128 + &snand_cap_program_load_x4),
1129 + SNAND_INFO("EM73D044VCH", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1b),
1130 + SNAND_MEMORG_2G_2K_64,
1131 + &snand_cap_read_from_cache_quad_q2d,
1132 + &snand_cap_program_load_x4),
1133 + SNAND_INFO("EM73D044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d),
1134 + SNAND_MEMORG_2G_2K_64,
1135 + &snand_cap_read_from_cache_quad_q2d,
1136 + &snand_cap_program_load_x4),
1137 + SNAND_INFO("EM73D044VCG", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1f),
1138 + SNAND_MEMORG_2G_2K_64,
1139 + &snand_cap_read_from_cache_quad_q2d,
1140 + &snand_cap_program_load_x4),
1141 + SNAND_INFO("EM73D044VCE", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x20),
1142 + SNAND_MEMORG_2G_2K_64,
1143 + &snand_cap_read_from_cache_quad_q2d,
1144 + &snand_cap_program_load_x4),
1145 + SNAND_INFO("EM73D044VCL", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2e),
1146 + SNAND_MEMORG_2G_2K_128,
1147 + &snand_cap_read_from_cache_quad_q2d,
1148 + &snand_cap_program_load_x4),
1149 + SNAND_INFO("EM73D044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x32),
1150 + SNAND_MEMORG_2G_2K_128,
1151 + &snand_cap_read_from_cache_quad_q2d,
1152 + &snand_cap_program_load_x4),
1153 + SNAND_INFO("EM73E044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x03),
1154 + SNAND_MEMORG_4G_4K_256,
1155 + &snand_cap_read_from_cache_quad_q2d,
1156 + &snand_cap_program_load_x4),
1157 + SNAND_INFO("EM73E044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0b),
1158 + SNAND_MEMORG_4G_4K_240,
1159 + &snand_cap_read_from_cache_quad_q2d,
1160 + &snand_cap_program_load_x4),
1161 + SNAND_INFO("EM73E044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x23),
1162 + SNAND_MEMORG_4G_4K_256,
1163 + &snand_cap_read_from_cache_quad_q2d,
1164 + &snand_cap_program_load_x4),
1165 + SNAND_INFO("EM73E044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2c),
1166 + SNAND_MEMORG_4G_4K_256,
1167 + &snand_cap_read_from_cache_quad_q2d,
1168 + &snand_cap_program_load_x4),
1169 + SNAND_INFO("EM73E044VCB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2f),
1170 + SNAND_MEMORG_4G_2K_128,
1171 + &snand_cap_read_from_cache_quad_q2d,
1172 + &snand_cap_program_load_x4),
1173 + SNAND_INFO("EM73F044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x24),
1174 + SNAND_MEMORG_8G_4K_256,
1175 + &snand_cap_read_from_cache_quad_q2d,
1176 + &snand_cap_program_load_x4),
1177 + SNAND_INFO("EM73F044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2d),
1178 + SNAND_MEMORG_8G_4K_256,
1179 + &snand_cap_read_from_cache_quad_q2d,
1180 + &snand_cap_program_load_x4),
1181 + SNAND_INFO("EM73E044SNE", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0e),
1182 + SNAND_MEMORG_8G_4K_256,
1183 + &snand_cap_read_from_cache_quad_q2d,
1184 + &snand_cap_program_load_x4),
1185 + SNAND_INFO("EM73C044SNG", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0c),
1186 + SNAND_MEMORG_1G_2K_120,
1187 + &snand_cap_read_from_cache_quad_q2d,
1188 + &snand_cap_program_load_x4),
1189 + SNAND_INFO("EM73D044VCN", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0f),
1190 + SNAND_MEMORG_2G_2K_64,
1191 + &snand_cap_read_from_cache_quad_q2d,
1192 + &snand_cap_program_load_x4),
1194 + SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
1195 + SNAND_MEMORG_1G_2K_64,
1196 + &snand_cap_read_from_cache_x4,
1197 + &snand_cap_program_load_x4),
1199 + SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
1200 + SNAND_MEMORG_1G_2K_128,
1201 + &snand_cap_read_from_cache_quad_q2d,
1202 + &snand_cap_program_load_x4),
1203 + SNAND_INFO("PN26G02A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe2),
1204 + SNAND_MEMORG_2G_2K_128,
1205 + &snand_cap_read_from_cache_quad_q2d,
1206 + &snand_cap_program_load_x4),
1208 + SNAND_INFO("IS37SML01G1", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x21),
1209 + SNAND_MEMORG_1G_2K_64,
1210 + &snand_cap_read_from_cache_x4,
1211 + &snand_cap_program_load_x4),
1213 + SNAND_INFO("ATO25D1GA", SNAND_ID(SNAND_ID_DYMMY, 0x9b, 0x12),
1214 + SNAND_MEMORG_1G_2K_64,
1215 + &snand_cap_read_from_cache_x4_only,
1216 + &snand_cap_program_load_x4),
1218 + SNAND_INFO("HYF1GQ4U", SNAND_ID(SNAND_ID_DYMMY, 0xc9, 0x51),
1219 + SNAND_MEMORG_1G_2K_128,
1220 + &snand_cap_read_from_cache_quad_q2d,
1221 + &snand_cap_program_load_x4),
1222 + SNAND_INFO("HYF2GQ4U", SNAND_ID(SNAND_ID_DYMMY, 0xc9, 0x52),
1223 + SNAND_MEMORG_2G_2K_128,
1224 + &snand_cap_read_from_cache_quad_q2d,
1225 + &snand_cap_program_load_x4),
1228 +static int mtk_snand_winbond_select_die(struct mtk_snand *snf, uint32_t dieidx)
1233 + snand_log_chip(snf->pdev, "Invalid die index %u\n", dieidx);
1237 + op[0] = SNAND_CMD_WINBOND_SELECT_DIE;
1238 + op[1] = (uint8_t)dieidx;
1240 + return mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0);
1243 +static int mtk_snand_micron_select_die(struct mtk_snand *snf, uint32_t dieidx)
1248 + snand_log_chip(snf->pdev, "Invalid die index %u\n", dieidx);
1252 + ret = mtk_snand_set_feature(snf, SNAND_FEATURE_MICRON_DIE_ADDR,
1253 + SNAND_MICRON_DIE_SEL_1);
1255 + snand_log_chip(snf->pdev,
1256 + "Failed to set die selection feature\n");
1263 +const struct snand_flash_info *snand_flash_id_lookup(enum snand_id_type type,
1264 + const uint8_t *id)
1266 + const struct snand_id *fid;
1269 + for (i = 0; i < ARRAY_SIZE(snand_flash_ids); i++) {
1270 + if (snand_flash_ids[i].id.type != type)
1273 + fid = &snand_flash_ids[i].id;
1274 + if (memcmp(fid->id, id, fid->len))
1277 + return &snand_flash_ids[i];
1283 +++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c
1285 +// SPDX-License-Identifier: GPL-2.0
1287 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
1289 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1292 +#include <common.h>
1294 +#include <malloc.h>
1295 +#include <mapmem.h>
1296 +#include <linux/mtd/mtd.h>
1297 +#include <watchdog.h>
1299 +#include "mtk-snand.h"
1301 +struct mtk_snand_mtd {
1302 + struct udevice *dev;
1303 + struct mtk_snand *snf;
1304 + struct mtk_snand_chip_info cinfo;
1305 + uint8_t *page_cache;
1308 +static const char snand_mtd_name_prefix[] = "spi-nand";
1310 +static u32 snandidx;
1312 +static inline struct mtk_snand_mtd *mtd_to_msm(struct mtd_info *mtd)
1317 +static int mtk_snand_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
1319 + struct mtk_snand_mtd *msm = mtd_to_msm(mtd);
1320 + u64 start_addr, end_addr;
1323 + /* Do not allow write past end of device */
1324 + if ((instr->addr + instr->len) > mtd->size) {
1325 + pr_debug("%s: attempt to erase beyond end of device\n",
1330 + start_addr = instr->addr & (~mtd->erasesize_mask);
1331 + end_addr = instr->addr + instr->len;
1332 + if (end_addr & mtd->erasesize_mask) {
1333 + end_addr = (end_addr + mtd->erasesize_mask) &
1334 + (~mtd->erasesize_mask);
1337 + instr->state = MTD_ERASING;
1339 + while (start_addr < end_addr) {
1342 + if (mtk_snand_block_isbad(msm->snf, start_addr)) {
1343 + if (!instr->scrub) {
1344 + instr->fail_addr = start_addr;
1350 + ret = mtk_snand_erase_block(msm->snf, start_addr);
1352 + instr->fail_addr = start_addr;
1356 + start_addr += mtd->erasesize;
1360 + instr->state = MTD_ERASE_DONE;
1362 + instr->state = MTD_ERASE_FAILED;
1369 +static int mtk_snand_mtd_read_data(struct mtk_snand_mtd *msm, uint64_t addr,
1370 + struct mtd_oob_ops *ops)
1372 + struct mtd_info *mtd = dev_get_uclass_priv(msm->dev);
1373 + size_t len, ooblen, maxooblen, chklen;
1374 + uint32_t col, ooboffs;
1375 + uint8_t *datcache, *oobcache;
1376 + bool ecc_failed = false, raw = ops->mode == MTD_OPS_RAW ? true : false;
1377 + int ret, max_bitflips = 0;
1379 + col = addr & mtd->writesize_mask;
1380 + addr &= ~mtd->writesize_mask;
1381 + maxooblen = mtd_oobavail(mtd, ops);
1382 + ooboffs = ops->ooboffs;
1383 + ooblen = ops->ooblen;
1386 + datcache = len ? msm->page_cache : NULL;
1387 + oobcache = ooblen ? msm->page_cache + mtd->writesize : NULL;
1389 + ops->oobretlen = 0;
1392 + while (len || ooblen) {
1395 + if (ops->mode == MTD_OPS_AUTO_OOB)
1396 + ret = mtk_snand_read_page_auto_oob(msm->snf, addr,
1397 + datcache, oobcache, maxooblen, NULL, raw);
1399 + ret = mtk_snand_read_page(msm->snf, addr, datcache,
1402 + if (ret < 0 && ret != -EBADMSG)
1405 + if (ret == -EBADMSG) {
1406 + mtd->ecc_stats.failed++;
1407 + ecc_failed = true;
1409 + mtd->ecc_stats.corrected += ret;
1410 + max_bitflips = max_t(int, ret, max_bitflips);
1413 + mtd->ecc_stats.corrected += ret;
1414 + max_bitflips = max_t(int, ret, max_bitflips);
1418 + chklen = mtd->writesize - col;
1422 + memcpy(ops->datbuf + ops->retlen, datcache + col,
1425 + col = 0; /* (col + chklen) % */
1426 + ops->retlen += chklen;
1431 + chklen = maxooblen - ooboffs;
1432 + if (chklen > ooblen)
1435 + memcpy(ops->oobbuf + ops->oobretlen, oobcache + ooboffs,
1438 + ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */
1439 + ops->oobretlen += chklen;
1442 + addr += mtd->writesize;
1445 + return ecc_failed ? -EBADMSG : max_bitflips;
1448 +static int mtk_snand_mtd_read_oob(struct mtd_info *mtd, loff_t from,
1449 + struct mtd_oob_ops *ops)
1451 + struct mtk_snand_mtd *msm = mtd_to_msm(mtd);
1452 + uint32_t maxooblen;
1454 + if (!ops->oobbuf && !ops->datbuf) {
1455 + if (ops->ooblen || ops->len)
1461 + switch (ops->mode) {
1462 + case MTD_OPS_PLACE_OOB:
1463 + case MTD_OPS_AUTO_OOB:
1467 + pr_debug("%s: unsupported oob mode: %u\n", __func__, ops->mode);
1471 + maxooblen = mtd_oobavail(mtd, ops);
1473 + /* Do not allow read past end of device */
1474 + if (ops->datbuf && (from + ops->len) > mtd->size) {
1475 + pr_debug("%s: attempt to read beyond end of device\n",
1480 + if (unlikely(ops->ooboffs >= maxooblen)) {
1481 + pr_debug("%s: attempt to start read outside oob\n",
1486 + if (unlikely(from >= mtd->size ||
1487 + ops->ooboffs + ops->ooblen > ((mtd->size >> mtd->writesize_shift) -
1488 + (from >> mtd->writesize_shift)) * maxooblen)) {
1489 + pr_debug("%s: attempt to read beyond end of device\n",
1494 + return mtk_snand_mtd_read_data(msm, from, ops);
1497 +static int mtk_snand_mtd_write_data(struct mtk_snand_mtd *msm, uint64_t addr,
1498 + struct mtd_oob_ops *ops)
1500 + struct mtd_info *mtd = dev_get_uclass_priv(msm->dev);
1501 + size_t len, ooblen, maxooblen, chklen, oobwrlen;
1502 + uint32_t col, ooboffs;
1503 + uint8_t *datcache, *oobcache;
1504 + bool raw = ops->mode == MTD_OPS_RAW ? true : false;
1507 + col = addr & mtd->writesize_mask;
1508 + addr &= ~mtd->writesize_mask;
1509 + maxooblen = mtd_oobavail(mtd, ops);
1510 + ooboffs = ops->ooboffs;
1511 + ooblen = ops->ooblen;
1514 + datcache = len ? msm->page_cache : NULL;
1515 + oobcache = ooblen ? msm->page_cache + mtd->writesize : NULL;
1517 + ops->oobretlen = 0;
1520 + while (len || ooblen) {
1525 + chklen = mtd->writesize - col;
1529 + memset(datcache, 0xff, col);
1530 + memcpy(datcache + col, ops->datbuf + ops->retlen,
1532 + memset(datcache + col + chklen, 0xff,
1533 + mtd->writesize - col - chklen);
1535 + col = 0; /* (col + chklen) % */
1536 + ops->retlen += chklen;
1542 + chklen = maxooblen - ooboffs;
1543 + if (chklen > ooblen)
1546 + memset(oobcache, 0xff, ooboffs);
1547 + memcpy(oobcache + ooboffs,
1548 + ops->oobbuf + ops->oobretlen, chklen);
1549 + memset(oobcache + ooboffs + chklen, 0xff,
1550 + mtd->oobsize - ooboffs - chklen);
1551 + oobwrlen = chklen + ooboffs;
1553 + ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */
1554 + ops->oobretlen += chklen;
1557 + if (ops->mode == MTD_OPS_AUTO_OOB)
1558 + ret = mtk_snand_write_page_auto_oob(msm->snf, addr,
1559 + datcache, oobcache, oobwrlen, NULL, raw);
1561 + ret = mtk_snand_write_page(msm->snf, addr, datcache,
1567 + addr += mtd->writesize;
1573 +static int mtk_snand_mtd_write_oob(struct mtd_info *mtd, loff_t to,
1574 + struct mtd_oob_ops *ops)
1576 + struct mtk_snand_mtd *msm = mtd_to_msm(mtd);
1577 + uint32_t maxooblen;
1579 + if (!ops->oobbuf && !ops->datbuf) {
1580 + if (ops->ooblen || ops->len)
1586 + switch (ops->mode) {
1587 + case MTD_OPS_PLACE_OOB:
1588 + case MTD_OPS_AUTO_OOB:
1592 + pr_debug("%s: unsupported oob mode: %u\n", __func__, ops->mode);
1596 + maxooblen = mtd_oobavail(mtd, ops);
1598 + /* Do not allow write past end of device */
1599 + if (ops->datbuf && (to + ops->len) > mtd->size) {
1600 + pr_debug("%s: attempt to write beyond end of device\n",
1605 + if (unlikely(ops->ooboffs >= maxooblen)) {
1606 + pr_debug("%s: attempt to start write outside oob\n",
1611 + if (unlikely(to >= mtd->size ||
1612 + ops->ooboffs + ops->ooblen > ((mtd->size >> mtd->writesize_shift) -
1613 + (to >> mtd->writesize_shift)) * maxooblen)) {
1614 + pr_debug("%s: attempt to write beyond end of device\n",
1619 + return mtk_snand_mtd_write_data(msm, to, ops);
1622 +static int mtk_snand_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
1623 + size_t *retlen, u_char *buf)
1625 + struct mtd_oob_ops ops = {
1626 + .mode = MTD_OPS_PLACE_OOB,
1632 + ret = mtk_snand_mtd_read_oob(mtd, from, &ops);
1635 + *retlen = ops.retlen;
1640 +static int mtk_snand_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
1641 + size_t *retlen, const u_char *buf)
1643 + struct mtd_oob_ops ops = {
1644 + .mode = MTD_OPS_PLACE_OOB,
1645 + .datbuf = (void *)buf,
1650 + ret = mtk_snand_mtd_write_oob(mtd, to, &ops);
1653 + *retlen = ops.retlen;
1658 +static int mtk_snand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
1660 + struct mtk_snand_mtd *msm = mtd_to_msm(mtd);
1662 + return mtk_snand_block_isbad(msm->snf, offs);
1665 +static int mtk_snand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)
1667 + struct mtk_snand_mtd *msm = mtd_to_msm(mtd);
1669 + return mtk_snand_block_markbad(msm->snf, offs);
1672 +static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section,
1673 + struct mtd_oob_region *oobecc)
1675 + struct mtk_snand_mtd *msm = mtd_to_msm(mtd);
1680 + oobecc->offset = msm->cinfo.fdm_size * msm->cinfo.num_sectors;
1681 + oobecc->length = mtd->oobsize - oobecc->offset;
1686 +static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section,
1687 + struct mtd_oob_region *oobfree)
1689 + struct mtk_snand_mtd *msm = mtd_to_msm(mtd);
1691 + if (section >= msm->cinfo.num_sectors)
1694 + oobfree->length = msm->cinfo.fdm_size - 1;
1695 + oobfree->offset = section * msm->cinfo.fdm_size + 1;
1700 +static const struct mtd_ooblayout_ops mtk_snand_ooblayout = {
1701 + .ecc = mtk_snand_ooblayout_ecc,
1702 + .rfree = mtk_snand_ooblayout_free,
1705 +static int mtk_snand_mtd_probe(struct udevice *dev)
1707 + struct mtk_snand_mtd *msm = dev_get_priv(dev);
1708 + struct mtd_info *mtd = dev_get_uclass_priv(dev);
1709 + struct mtk_snand_platdata mtk_snand_pdata = {};
1714 + base = dev_read_addr_name(dev, "nfi");
1715 + if (base == FDT_ADDR_T_NONE)
1717 + mtk_snand_pdata.nfi_base = map_sysmem(base, 0);
1719 + base = dev_read_addr_name(dev, "ecc");
1720 + if (base == FDT_ADDR_T_NONE)
1722 + mtk_snand_pdata.ecc_base = map_sysmem(base, 0);
1724 + mtk_snand_pdata.soc = dev_get_driver_data(dev);
1725 + mtk_snand_pdata.quad_spi = dev_read_bool(dev, "quad-spi");
1727 + ret = mtk_snand_init(NULL, &mtk_snand_pdata, &msm->snf);
1731 + mtk_snand_get_chip_info(msm->snf, &msm->cinfo);
1733 + msm->page_cache = malloc(msm->cinfo.pagesize + msm->cinfo.sparesize);
1734 + if (!msm->page_cache) {
1735 + printf("%s: failed to allocate memory for page cache\n",
1741 + namelen = sizeof(snand_mtd_name_prefix) + 12;
1743 + mtd->name = malloc(namelen);
1745 + printf("%s: failed to allocate memory for MTD name\n",
1753 + snprintf(mtd->name, namelen, "%s%u", snand_mtd_name_prefix, snandidx++);
1757 + mtd->type = MTD_NANDFLASH;
1758 + mtd->flags = MTD_CAP_NANDFLASH;
1760 + mtd->size = msm->cinfo.chipsize;
1761 + mtd->erasesize = msm->cinfo.blocksize;
1762 + mtd->writesize = msm->cinfo.pagesize;
1763 + mtd->writebufsize = mtd->writesize;
1764 + mtd->oobsize = msm->cinfo.sparesize;
1765 + mtd->oobavail = msm->cinfo.num_sectors * (msm->cinfo.fdm_size - 1);
1767 + mtd->ooblayout = &mtk_snand_ooblayout;
1769 + mtd->ecc_strength = msm->cinfo.ecc_strength;
1770 + mtd->bitflip_threshold = (mtd->ecc_strength * 3) / 4;
1771 + mtd->ecc_step_size = msm->cinfo.sector_size;
1773 + mtd->_read = mtk_snand_mtd_read;
1774 + mtd->_write = mtk_snand_mtd_write;
1775 + mtd->_erase = mtk_snand_mtd_erase;
1776 + mtd->_read_oob = mtk_snand_mtd_read_oob;
1777 + mtd->_write_oob = mtk_snand_mtd_write_oob;
1778 + mtd->_block_isbad = mtk_snand_mtd_block_isbad;
1779 + mtd->_block_markbad = mtk_snand_mtd_block_markbad;
1781 + ret = add_mtd_device(mtd);
1783 + printf("%s: failed to add SPI-NAND MTD device\n", __func__);
1788 + printf("SPI-NAND: %s (%lluMB)\n", msm->cinfo.model,
1789 + msm->cinfo.chipsize >> 20);
1797 + free(msm->page_cache);
1800 + mtk_snand_cleanup(msm->snf);
1805 +static const struct udevice_id mtk_snand_ids[] = {
1806 + { .compatible = "mediatek,mt7622-snand", .data = SNAND_SOC_MT7622 },
1807 + { .compatible = "mediatek,mt7629-snand", .data = SNAND_SOC_MT7629 },
1808 + { .compatible = "mediatek,mt7981-snand", .data = SNAND_SOC_MT7981 },
1809 + { .compatible = "mediatek,mt7986-snand", .data = SNAND_SOC_MT7986 },
1810 + { /* sentinel */ },
1813 +U_BOOT_DRIVER(spinand) = {
1814 + .name = "mtk-snand",
1816 + .of_match = mtk_snand_ids,
1817 + .priv_auto = sizeof(struct mtk_snand_mtd),
1818 + .probe = mtk_snand_mtd_probe,
1821 +++ b/drivers/mtd/mtk-snand/mtk-snand-os.c
1823 +// SPDX-License-Identifier: GPL-2.0
1825 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
1827 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1830 +#include "mtk-snand-def.h"
1832 +int mtk_snand_log(struct mtk_snand_plat_dev *pdev,
1833 + enum mtk_snand_log_category cat, const char *fmt, ...)
1835 + const char *catname = "";
1840 + case SNAND_LOG_NFI:
1841 + catname = "NFI: ";
1843 + case SNAND_LOG_SNFI:
1844 + catname = "SNFI: ";
1846 + case SNAND_LOG_ECC:
1847 + catname = "ECC: ";
1853 + puts("SPI-NAND: ");
1856 + va_start(ap, fmt);
1857 + ret = vprintf(fmt, ap);
1863 +++ b/drivers/mtd/mtk-snand/mtk-snand-os.h
1865 +/* SPDX-License-Identifier: GPL-2.0 */
1867 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
1869 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1872 +#ifndef _MTK_SNAND_OS_H_
1873 +#define _MTK_SNAND_OS_H_
1875 +#include <common.h>
1876 +#include <cpu_func.h>
1879 +#include <malloc.h>
1880 +#include <stdbool.h>
1881 +#include <stdarg.h>
1882 +#include <linux/types.h>
1883 +#include <asm/io.h>
1884 +#include <linux/bitops.h>
1885 +#include <linux/sizes.h>
1886 +#include <linux/iopoll.h>
1888 +#ifndef ARCH_DMA_MINALIGN
1889 +#define ARCH_DMA_MINALIGN 64
1892 +struct mtk_snand_plat_dev {
1896 +/* Polling helpers */
1897 +#define read16_poll_timeout(addr, val, cond, sleep_us, timeout_us) \
1898 + readw_poll_timeout((addr), (val), (cond), (timeout_us))
1900 +#define read32_poll_timeout(addr, val, cond, sleep_us, timeout_us) \
1901 + readl_poll_timeout((addr), (val), (cond), (timeout_us))
1903 +/* Timer helpers */
1904 +typedef uint64_t mtk_snand_time_t;
1906 +static inline mtk_snand_time_t timer_get_ticks(void)
1908 + return get_ticks();
1911 +static inline mtk_snand_time_t timer_time_to_tick(uint32_t timeout_us)
1913 + return usec_to_tick(timeout_us);
1916 +static inline bool timer_is_timeout(mtk_snand_time_t start_tick,
1917 + mtk_snand_time_t timeout_tick)
1919 + return get_ticks() - start_tick > timeout_tick;
1922 +/* Memory helpers */
1923 +static inline void *generic_mem_alloc(struct mtk_snand_plat_dev *pdev,
1926 + return calloc(1, size);
1929 +static inline void generic_mem_free(struct mtk_snand_plat_dev *pdev, void *ptr)
1934 +static inline void *dma_mem_alloc(struct mtk_snand_plat_dev *pdev, size_t size)
1936 + return memalign(ARCH_DMA_MINALIGN, size);
1939 +static inline void dma_mem_free(struct mtk_snand_plat_dev *pdev, void *ptr)
1944 +static inline int dma_mem_map(struct mtk_snand_plat_dev *pdev, void *vaddr,
1945 + uintptr_t *dma_addr, size_t size, bool to_device)
1947 + size_t cachelen = roundup(size, ARCH_DMA_MINALIGN);
1948 + uintptr_t endaddr = (uintptr_t)vaddr + cachelen;
1951 + flush_dcache_range((uintptr_t)vaddr, endaddr);
1953 + invalidate_dcache_range((uintptr_t)vaddr, endaddr);
1955 + *dma_addr = (uintptr_t)vaddr;
1960 +static inline void dma_mem_unmap(struct mtk_snand_plat_dev *pdev,
1961 + uintptr_t dma_addr, size_t size,
1966 +/* Interrupt helpers */
1967 +static inline void irq_completion_done(struct mtk_snand_plat_dev *pdev)
1971 +static inline void irq_completion_init(struct mtk_snand_plat_dev *pdev)
1975 +static inline int irq_completion_wait(struct mtk_snand_plat_dev *pdev,
1976 + void __iomem *reg, uint32_t bit,
1977 + uint32_t timeout_us)
1981 + return read32_poll_timeout(reg, val, val & bit, 0, timeout_us);
1984 +#endif /* _MTK_SNAND_OS_H_ */
1986 +++ b/drivers/mtd/mtk-snand/mtk-snand.c
1988 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
1990 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
1992 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1995 +#include "mtk-snand-def.h"
1997 +/* NFI registers */
1998 +#define NFI_CNFG 0x000
1999 +#define CNFG_OP_MODE_S 12
2000 +#define CNFG_OP_MODE_CUST 6
2001 +#define CNFG_OP_MODE_PROGRAM 3
2002 +#define CNFG_AUTO_FMT_EN BIT(9)
2003 +#define CNFG_HW_ECC_EN BIT(8)
2004 +#define CNFG_DMA_BURST_EN BIT(2)
2005 +#define CNFG_READ_MODE BIT(1)
2006 +#define CNFG_DMA_MODE BIT(0)
2008 +#define NFI_PAGEFMT 0x0004
2009 +#define NFI_SPARE_SIZE_LS_S 16
2010 +#define NFI_FDM_ECC_NUM_S 12
2011 +#define NFI_FDM_NUM_S 8
2012 +#define NFI_SPARE_SIZE_S 4
2013 +#define NFI_SEC_SEL_512 BIT(2)
2014 +#define NFI_PAGE_SIZE_S 0
2015 +#define NFI_PAGE_SIZE_512_2K 0
2016 +#define NFI_PAGE_SIZE_2K_4K 1
2017 +#define NFI_PAGE_SIZE_4K_8K 2
2018 +#define NFI_PAGE_SIZE_8K_16K 3
2020 +#define NFI_CON 0x008
2021 +#define CON_SEC_NUM_S 12
2022 +#define CON_BWR BIT(9)
2023 +#define CON_BRD BIT(8)
2024 +#define CON_NFI_RST BIT(1)
2025 +#define CON_FIFO_FLUSH BIT(0)
2027 +#define NFI_INTR_EN 0x010
2028 +#define NFI_INTR_STA 0x014
2029 +#define NFI_IRQ_INTR_EN BIT(31)
2030 +#define NFI_IRQ_CUS_READ BIT(8)
2031 +#define NFI_IRQ_CUS_PG BIT(7)
2033 +#define NFI_CMD 0x020
2035 +#define NFI_STRDATA 0x040
2036 +#define STR_DATA BIT(0)
2038 +#define NFI_STA 0x060
2039 +#define NFI_NAND_FSM GENMASK(28, 24)
2040 +#define NFI_FSM GENMASK(19, 16)
2041 +#define READ_EMPTY BIT(12)
2043 +#define NFI_FIFOSTA 0x064
2044 +#define FIFO_WR_REMAIN_S 8
2045 +#define FIFO_RD_REMAIN_S 0
2047 +#define NFI_ADDRCNTR 0x070
2048 +#define SEC_CNTR GENMASK(16, 12)
2049 +#define SEC_CNTR_S 12
2050 +#define NFI_SEC_CNTR(val) (((val) & SEC_CNTR) >> SEC_CNTR_S)
2052 +#define NFI_STRADDR 0x080
2054 +#define NFI_BYTELEN 0x084
2055 +#define BUS_SEC_CNTR(val) (((val) & SEC_CNTR) >> SEC_CNTR_S)
2057 +#define NFI_FDM0L 0x0a0
2058 +#define NFI_FDM0M 0x0a4
2059 +#define NFI_FDML(n) (NFI_FDM0L + (n) * 8)
2060 +#define NFI_FDMM(n) (NFI_FDM0M + (n) * 8)
2062 +#define NFI_DEBUG_CON1 0x220
2063 +#define WBUF_EN BIT(2)
2065 +#define NFI_MASTERSTA 0x224
2066 +#define MAS_ADDR GENMASK(11, 9)
2067 +#define MAS_RD GENMASK(8, 6)
2068 +#define MAS_WR GENMASK(5, 3)
2069 +#define MAS_RDDLY GENMASK(2, 0)
2070 +#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)
2071 +#define AHB_BUS_BUSY BIT(1)
2072 +#define BUS_BUSY BIT(0)
2073 +#define NFI_MASTERSTA_MASK_7981 (AHB_BUS_BUSY | BUS_BUSY)
2074 +#define NFI_MASTERSTA_MASK_7986 (AHB_BUS_BUSY | BUS_BUSY)
2076 +/* SNFI registers */
2077 +#define SNF_MAC_CTL 0x500
2078 +#define MAC_XIO_SEL BIT(4)
2079 +#define SF_MAC_EN BIT(3)
2080 +#define SF_TRIG BIT(2)
2081 +#define WIP_READY BIT(1)
2084 +#define SNF_MAC_OUTL 0x504
2085 +#define SNF_MAC_INL 0x508
2087 +#define SNF_RD_CTL2 0x510
2088 +#define DATA_READ_DUMMY_S 8
2089 +#define DATA_READ_CMD_S 0
2091 +#define SNF_RD_CTL3 0x514
2093 +#define SNF_PG_CTL1 0x524
2094 +#define PG_LOAD_CMD_S 8
2096 +#define SNF_PG_CTL2 0x528
2098 +#define SNF_MISC_CTL 0x538
2099 +#define SW_RST BIT(28)
2100 +#define FIFO_RD_LTC_S 25
2101 +#define PG_LOAD_X4_EN BIT(20)
2102 +#define DATA_READ_MODE_S 16
2103 +#define DATA_READ_MODE GENMASK(18, 16)
2104 +#define DATA_READ_MODE_X1 0
2105 +#define DATA_READ_MODE_X2 1
2106 +#define DATA_READ_MODE_X4 2
2107 +#define DATA_READ_MODE_DUAL 5
2108 +#define DATA_READ_MODE_QUAD 6
2109 +#define LATCH_LAT_S 8
2110 +#define LATCH_LAT GENMASK(9, 8)
2111 +#define PG_LOAD_CUSTOM_EN BIT(7)
2112 +#define DATARD_CUSTOM_EN BIT(6)
2113 +#define CS_DESELECT_CYC_S 0
2115 +#define SNF_MISC_CTL2 0x53c
2116 +#define PROGRAM_LOAD_BYTE_NUM_S 16
2117 +#define READ_DATA_BYTE_NUM_S 11
2119 +#define SNF_DLY_CTL3 0x548
2120 +#define SFCK_SAM_DLY_S 0
2122 +#define SNF_STA_CTL1 0x550
2123 +#define CUS_PG_DONE BIT(28)
2124 +#define CUS_READ_DONE BIT(27)
2125 +#define SPI_STATE_S 0
2126 +#define SPI_STATE GENMASK(3, 0)
2128 +#define SNF_CFG 0x55c
2129 +#define SPI_MODE BIT(0)
2131 +#define SNF_GPRAM 0x800
2132 +#define SNF_GPRAM_SIZE 0xa0
2134 +#define SNFI_POLL_INTERVAL 1000000
2136 +static const uint8_t mt7622_spare_sizes[] = { 16, 26, 27, 28 };
2138 +static const uint8_t mt7981_spare_sizes[] = {
2139 + 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64,
2143 +static const uint8_t mt7986_spare_sizes[] = {
2144 + 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64,
2148 +static const struct mtk_snand_soc_data mtk_snand_socs[__SNAND_SOC_MAX] = {
2149 + [SNAND_SOC_MT7622] = {
2150 + .sector_size = 512,
2153 + .fdm_ecc_size = 1,
2155 + .bbm_swap = false,
2156 + .empty_page_check = false,
2157 + .mastersta_mask = NFI_MASTERSTA_MASK_7622,
2158 + .spare_sizes = mt7622_spare_sizes,
2159 + .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes),
2161 + .sample_delay = 40
2163 + [SNAND_SOC_MT7629] = {
2164 + .sector_size = 512,
2167 + .fdm_ecc_size = 1,
2170 + .empty_page_check = false,
2171 + .mastersta_mask = NFI_MASTERSTA_MASK_7622,
2172 + .spare_sizes = mt7622_spare_sizes,
2173 + .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes),
2175 + .sample_delay = 40
2177 + [SNAND_SOC_MT7981] = {
2178 + .sector_size = 1024,
2179 + .max_sectors = 16,
2181 + .fdm_ecc_size = 1,
2184 + .empty_page_check = true,
2185 + .mastersta_mask = NFI_MASTERSTA_MASK_7981,
2186 + .spare_sizes = mt7981_spare_sizes,
2187 + .num_spare_size = ARRAY_SIZE(mt7981_spare_sizes),
2189 + .sample_delay = 40
2191 + [SNAND_SOC_MT7986] = {
2192 + .sector_size = 1024,
2193 + .max_sectors = 16,
2195 + .fdm_ecc_size = 1,
2198 + .empty_page_check = true,
2199 + .mastersta_mask = NFI_MASTERSTA_MASK_7986,
2200 + .spare_sizes = mt7986_spare_sizes,
2201 + .num_spare_size = ARRAY_SIZE(mt7986_spare_sizes),
2203 + .sample_delay = 40
2207 +static inline uint32_t nfi_read32(struct mtk_snand *snf, uint32_t reg)
2209 + return readl(snf->nfi_base + reg);
2212 +static inline void nfi_write32(struct mtk_snand *snf, uint32_t reg,
2215 + writel(val, snf->nfi_base + reg);
2218 +static inline void nfi_write16(struct mtk_snand *snf, uint32_t reg,
2221 + writew(val, snf->nfi_base + reg);
2224 +static inline void nfi_rmw32(struct mtk_snand *snf, uint32_t reg, uint32_t clr,
2229 + val = readl(snf->nfi_base + reg);
2232 + writel(val, snf->nfi_base + reg);
2235 +static void nfi_write_data(struct mtk_snand *snf, uint32_t reg,
2236 + const uint8_t *data, uint32_t len)
2238 + uint32_t i, val = 0, es = sizeof(uint32_t);
2240 + for (i = reg; i < reg + len; i++) {
2241 + val |= ((uint32_t)*data++) << (8 * (i % es));
2243 + if (i % es == es - 1 || i == reg + len - 1) {
2244 + nfi_write32(snf, i & ~(es - 1), val);
2250 +static void nfi_read_data(struct mtk_snand *snf, uint32_t reg, uint8_t *data,
2253 + uint32_t i, val = 0, es = sizeof(uint32_t);
2255 + for (i = reg; i < reg + len; i++) {
2256 + if (i == reg || i % es == 0)
2257 + val = nfi_read32(snf, i & ~(es - 1));
2259 + *data++ = (uint8_t)(val >> (8 * (i % es)));
2263 +static inline void do_bm_swap(uint8_t *bm1, uint8_t *bm2)
2265 + uint8_t tmp = *bm1;
2270 +static void mtk_snand_bm_swap_raw(struct mtk_snand *snf)
2272 + uint32_t fdm_bbm_pos;
2274 + if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1)
2277 + fdm_bbm_pos = (snf->ecc_steps - 1) * snf->raw_sector_size +
2278 + snf->nfi_soc->sector_size;
2279 + do_bm_swap(&snf->page_cache[fdm_bbm_pos],
2280 + &snf->page_cache[snf->writesize]);
2283 +static void mtk_snand_bm_swap(struct mtk_snand *snf)
2285 + uint32_t buf_bbm_pos, fdm_bbm_pos;
2287 + if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1)
2290 + buf_bbm_pos = snf->writesize -
2291 + (snf->ecc_steps - 1) * snf->spare_per_sector;
2292 + fdm_bbm_pos = snf->writesize +
2293 + (snf->ecc_steps - 1) * snf->nfi_soc->fdm_size;
2294 + do_bm_swap(&snf->page_cache[fdm_bbm_pos],
2295 + &snf->page_cache[buf_bbm_pos]);
2298 +static void mtk_snand_fdm_bm_swap_raw(struct mtk_snand *snf)
2300 + uint32_t fdm_bbm_pos1, fdm_bbm_pos2;
2302 + if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1)
2305 + fdm_bbm_pos1 = snf->nfi_soc->sector_size;
2306 + fdm_bbm_pos2 = (snf->ecc_steps - 1) * snf->raw_sector_size +
2307 + snf->nfi_soc->sector_size;
2308 + do_bm_swap(&snf->page_cache[fdm_bbm_pos1],
2309 + &snf->page_cache[fdm_bbm_pos2]);
2312 +static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf)
2314 + uint32_t fdm_bbm_pos1, fdm_bbm_pos2;
2316 + if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1)
2319 + fdm_bbm_pos1 = snf->writesize;
2320 + fdm_bbm_pos2 = snf->writesize +
2321 + (snf->ecc_steps - 1) * snf->nfi_soc->fdm_size;
2322 + do_bm_swap(&snf->page_cache[fdm_bbm_pos1],
2323 + &snf->page_cache[fdm_bbm_pos2]);
2326 +static int mtk_nfi_reset(struct mtk_snand *snf)
2328 + uint32_t val, fifo_mask;
2331 + nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);
2333 + ret = read16_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
2334 + !(val & snf->nfi_soc->mastersta_mask), 0,
2335 + SNFI_POLL_INTERVAL);
2337 + snand_log_nfi(snf->pdev,
2338 + "NFI master is still busy after reset\n");
2342 + ret = read32_poll_timeout(snf->nfi_base + NFI_STA, val,
2343 + !(val & (NFI_FSM | NFI_NAND_FSM)), 0,
2344 + SNFI_POLL_INTERVAL);
2346 + snand_log_nfi(snf->pdev, "Failed to reset NFI\n");
2350 + fifo_mask = ((snf->nfi_soc->fifo_size - 1) << FIFO_RD_REMAIN_S) |
2351 + ((snf->nfi_soc->fifo_size - 1) << FIFO_WR_REMAIN_S);
2352 + ret = read16_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val,
2353 + !(val & fifo_mask), 0, SNFI_POLL_INTERVAL);
2355 + snand_log_nfi(snf->pdev, "NFI FIFOs are not empty\n");
2362 +static int mtk_snand_mac_reset(struct mtk_snand *snf)
2367 + nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST);
2369 + ret = read32_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val,
2370 + !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL);
2372 + snand_log_snfi(snf->pdev, "Failed to reset SNFI MAC\n");
2374 + nfi_write32(snf, SNF_MISC_CTL, (2 << FIFO_RD_LTC_S) |
2375 + (10 << CS_DESELECT_CYC_S) | (snf->nfi_soc->latch_lat << LATCH_LAT_S));
2380 +static int mtk_snand_mac_trigger(struct mtk_snand *snf, uint32_t outlen,
2386 + nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN);
2387 + nfi_write32(snf, SNF_MAC_OUTL, outlen);
2388 + nfi_write32(snf, SNF_MAC_INL, inlen);
2390 + nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG);
2392 + ret = read32_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,
2393 + val & WIP_READY, 0, SNFI_POLL_INTERVAL);
2395 + snand_log_snfi(snf->pdev, "Timed out waiting for WIP_READY\n");
2399 + ret = read32_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,
2400 + !(val & WIP), 0, SNFI_POLL_INTERVAL);
2402 + snand_log_snfi(snf->pdev,
2403 + "Timed out waiting for WIP cleared\n");
2407 + nfi_write32(snf, SNF_MAC_CTL, 0);
2412 +int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen,
2413 + uint8_t *in, uint32_t inlen)
2417 + if (outlen + inlen > SNF_GPRAM_SIZE)
2420 + mtk_snand_mac_reset(snf);
2422 + nfi_write_data(snf, SNF_GPRAM, out, outlen);
2424 + ret = mtk_snand_mac_trigger(snf, outlen, inlen);
2431 + nfi_read_data(snf, SNF_GPRAM + outlen, in, inlen);
2436 +static int mtk_snand_get_feature(struct mtk_snand *snf, uint32_t addr)
2438 + uint8_t op[2], val;
2441 + op[0] = SNAND_CMD_GET_FEATURE;
2442 + op[1] = (uint8_t)addr;
2444 + ret = mtk_snand_mac_io(snf, op, sizeof(op), &val, 1);
2451 +int mtk_snand_set_feature(struct mtk_snand *snf, uint32_t addr, uint32_t val)
2455 + op[0] = SNAND_CMD_SET_FEATURE;
2456 + op[1] = (uint8_t)addr;
2457 + op[2] = (uint8_t)val;
2459 + return mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0);
2462 +static int mtk_snand_poll_status(struct mtk_snand *snf, uint32_t wait_us)
2465 + mtk_snand_time_t time_start, tmo;
2467 + time_start = timer_get_ticks();
2468 + tmo = timer_time_to_tick(wait_us);
2471 + val = mtk_snand_get_feature(snf, SNAND_FEATURE_STATUS_ADDR);
2472 + if (!(val & SNAND_STATUS_OIP))
2473 + return val & (SNAND_STATUS_ERASE_FAIL |
2474 + SNAND_STATUS_PROGRAM_FAIL);
2475 + } while (!timer_is_timeout(time_start, tmo));
2477 + return -ETIMEDOUT;
2480 +int mtk_snand_chip_reset(struct mtk_snand *snf)
2482 + uint8_t op = SNAND_CMD_RESET;
2485 + ret = mtk_snand_mac_io(snf, &op, 1, NULL, 0);
2489 + ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL);
2496 +static int mtk_snand_config_feature(struct mtk_snand *snf, uint8_t clr,
2502 + val = mtk_snand_get_feature(snf, SNAND_FEATURE_CONFIG_ADDR);
2504 + snand_log_chip(snf->pdev,
2505 + "Failed to get configuration feature\n");
2509 + newval = (val & (~clr)) | set;
2511 + if (newval == val)
2514 + ret = mtk_snand_set_feature(snf, SNAND_FEATURE_CONFIG_ADDR,
2517 + snand_log_chip(snf->pdev,
2518 + "Failed to set configuration feature\n");
2522 + val = mtk_snand_get_feature(snf, SNAND_FEATURE_CONFIG_ADDR);
2524 + snand_log_chip(snf->pdev,
2525 + "Failed to get configuration feature\n");
2529 + if (newval != val)
2535 +static int mtk_snand_ondie_ecc_control(struct mtk_snand *snf, bool enable)
2540 + ret = mtk_snand_config_feature(snf, 0, SNAND_FEATURE_ECC_EN);
2542 + ret = mtk_snand_config_feature(snf, SNAND_FEATURE_ECC_EN, 0);
2545 + snand_log_chip(snf->pdev, "Failed to %s On-Die ECC engine\n",
2546 + enable ? "enable" : "disable");
2552 +static int mtk_snand_qspi_control(struct mtk_snand *snf, bool enable)
2557 + ret = mtk_snand_config_feature(snf, 0,
2558 + SNAND_FEATURE_QUAD_ENABLE);
2560 + ret = mtk_snand_config_feature(snf,
2561 + SNAND_FEATURE_QUAD_ENABLE, 0);
2565 + snand_log_chip(snf->pdev, "Failed to %s quad spi\n",
2566 + enable ? "enable" : "disable");
2572 +static int mtk_snand_unlock(struct mtk_snand *snf)
2576 + ret = mtk_snand_set_feature(snf, SNAND_FEATURE_PROTECT_ADDR, 0);
2578 + snand_log_chip(snf->pdev, "Failed to set protection feature\n");
2585 +static int mtk_snand_write_enable(struct mtk_snand *snf)
2587 + uint8_t op = SNAND_CMD_WRITE_ENABLE;
2590 + ret = mtk_snand_mac_io(snf, &op, 1, NULL, 0);
2594 + val = mtk_snand_get_feature(snf, SNAND_FEATURE_STATUS_ADDR);
2598 + if (val & SNAND_STATUS_WEL)
2601 + snand_log_chip(snf->pdev, "Failed to send write-enable command\n");
2606 +static int mtk_snand_select_die(struct mtk_snand *snf, uint32_t dieidx)
2608 + if (!snf->select_die)
2611 + return snf->select_die(snf, dieidx);
2614 +static uint64_t mtk_snand_select_die_address(struct mtk_snand *snf,
2619 + if (!snf->select_die)
2622 + dieidx = addr >> snf->die_shift;
2624 + mtk_snand_select_die(snf, dieidx);
2626 + return addr & snf->die_mask;
2629 +static uint32_t mtk_snand_get_plane_address(struct mtk_snand *snf,
2632 + uint32_t pages_per_block;
2634 + pages_per_block = 1 << (snf->erasesize_shift - snf->writesize_shift);
2636 + if (page & pages_per_block)
2637 + return 1 << (snf->writesize_shift + 1);
2642 +static int mtk_snand_page_op(struct mtk_snand *snf, uint32_t page, uint8_t cmd)
2647 + op[1] = (page >> 16) & 0xff;
2648 + op[2] = (page >> 8) & 0xff;
2649 + op[3] = page & 0xff;
2651 + return mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0);
2654 +static void mtk_snand_read_fdm(struct mtk_snand *snf, uint8_t *buf)
2656 + uint32_t vall, valm;
2657 + uint8_t *oobptr = buf;
2660 + for (i = 0; i < snf->ecc_steps; i++) {
2661 + vall = nfi_read32(snf, NFI_FDML(i));
2662 + valm = nfi_read32(snf, NFI_FDMM(i));
2664 + for (j = 0; j < snf->nfi_soc->fdm_size; j++)
2665 + oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
2667 + oobptr += snf->nfi_soc->fdm_size;
2671 +static int mtk_snand_read_ecc_parity(struct mtk_snand *snf, uint32_t page,
2672 + uint32_t sect, uint8_t *oob)
2674 + uint32_t ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size;
2675 + uint32_t coladdr, raw_offs, offs;
2678 + if (sizeof(op) + ecc_bytes > SNF_GPRAM_SIZE) {
2679 + snand_log_snfi(snf->pdev,
2680 + "ECC parity size does not fit the GPRAM\n");
2684 + raw_offs = sect * snf->raw_sector_size + snf->nfi_soc->sector_size +
2685 + snf->nfi_soc->fdm_size;
2686 + offs = snf->ecc_steps * snf->nfi_soc->fdm_size + sect * ecc_bytes;
2688 + /* Column address with plane bit */
2689 + coladdr = raw_offs | mtk_snand_get_plane_address(snf, page);
2691 + op[0] = SNAND_CMD_READ_FROM_CACHE;
2692 + op[1] = (coladdr >> 8) & 0xff;
2693 + op[2] = coladdr & 0xff;
2696 + return mtk_snand_mac_io(snf, op, sizeof(op), oob + offs, ecc_bytes);
2699 +static int mtk_snand_check_ecc_result(struct mtk_snand *snf, uint32_t page)
2701 + uint8_t *oob = snf->page_cache + snf->writesize;
2702 + int i, rc, ret = 0, max_bitflips = 0;
2704 + for (i = 0; i < snf->ecc_steps; i++) {
2705 + if (snf->sect_bf[i] >= 0) {
2706 + if (snf->sect_bf[i] > max_bitflips)
2707 + max_bitflips = snf->sect_bf[i];
2711 + rc = mtk_snand_read_ecc_parity(snf, page, i, oob);
2715 + rc = mtk_ecc_fixup_empty_sector(snf, i);
2719 + snand_log_ecc(snf->pdev,
2720 + "Uncorrectable bitflips in page %u sect %u\n",
2723 + snf->sect_bf[i] = rc;
2725 + if (snf->sect_bf[i] > max_bitflips)
2726 + max_bitflips = snf->sect_bf[i];
2728 + snand_log_ecc(snf->pdev,
2729 + "%u bitflip%s corrected in page %u sect %u\n",
2730 + rc, rc > 1 ? "s" : "", page, i);
2732 + snf->sect_bf[i] = 0;
2736 + return ret ? ret : max_bitflips;
2739 +static int mtk_snand_read_cache(struct mtk_snand *snf, uint32_t page, bool raw)
2741 + uint32_t coladdr, rwbytes, mode, len, val;
2742 + uintptr_t dma_addr;
2745 + /* Column address with plane bit */
2746 + coladdr = mtk_snand_get_plane_address(snf, page);
2748 + mtk_snand_mac_reset(snf);
2749 + mtk_nfi_reset(snf);
2751 + /* Command and dummy cycles */
2752 + nfi_write32(snf, SNF_RD_CTL2,
2753 + ((uint32_t)snf->dummy_rfc << DATA_READ_DUMMY_S) |
2754 + (snf->opcode_rfc << DATA_READ_CMD_S));
2756 + /* Column address */
2757 + nfi_write32(snf, SNF_RD_CTL3, coladdr);
2759 + /* Set read mode */
2760 + mode = (uint32_t)snf->mode_rfc << DATA_READ_MODE_S;
2761 + nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE,
2762 + mode | DATARD_CUSTOM_EN | (snf->nfi_soc->latch_lat << LATCH_LAT_S));
2764 + /* Set bytes to read */
2765 + rwbytes = snf->ecc_steps * snf->raw_sector_size;
2766 + nfi_write32(snf, SNF_MISC_CTL2, (rwbytes << PROGRAM_LOAD_BYTE_NUM_S) |
2769 + /* NFI read prepare */
2770 + mode = raw ? 0 : CNFG_HW_ECC_EN | CNFG_AUTO_FMT_EN;
2771 + nfi_write16(snf, NFI_CNFG, (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) |
2772 + CNFG_DMA_BURST_EN | CNFG_READ_MODE | CNFG_DMA_MODE | mode);
2774 + nfi_write32(snf, NFI_CON, (snf->ecc_steps << CON_SEC_NUM_S));
2776 + /* Prepare for DMA read */
2777 + len = snf->writesize + snf->oobsize;
2778 + ret = dma_mem_map(snf->pdev, snf->page_cache, &dma_addr, len, false);
2780 + snand_log_nfi(snf->pdev,
2781 + "DMA map from device failed with %d\n", ret);
2785 + nfi_write32(snf, NFI_STRADDR, (uint32_t)dma_addr);
2788 + mtk_snand_ecc_decoder_start(snf);
2790 + /* Prepare for custom read interrupt */
2791 + nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ);
2792 + irq_completion_init(snf->pdev);
2794 + /* Trigger NFI into custom mode */
2795 + nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ);
2797 + /* Start DMA read */
2798 + nfi_rmw32(snf, NFI_CON, 0, CON_BRD);
2799 + nfi_write16(snf, NFI_STRDATA, STR_DATA);
2801 + /* Wait for operation finished */
2802 + ret = irq_completion_wait(snf->pdev, snf->nfi_base + SNF_STA_CTL1,
2803 + CUS_READ_DONE, SNFI_POLL_INTERVAL);
2805 + snand_log_nfi(snf->pdev,
2806 + "DMA timed out for reading from cache\n");
2810 + /* Wait for BUS_SEC_CNTR returning expected value */
2811 + ret = read32_poll_timeout(snf->nfi_base + NFI_BYTELEN, val,
2812 + BUS_SEC_CNTR(val) >= snf->ecc_steps,
2813 + 0, SNFI_POLL_INTERVAL);
2815 + snand_log_nfi(snf->pdev,
2816 + "Timed out waiting for BUS_SEC_CNTR\n");
2820 + /* Wait for bus becoming idle */
2821 + ret = read32_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
2822 + !(val & snf->nfi_soc->mastersta_mask),
2823 + 0, SNFI_POLL_INTERVAL);
2825 + snand_log_nfi(snf->pdev,
2826 + "Timed out waiting for bus becoming idle\n");
2831 + ret = mtk_ecc_wait_decoder_done(snf);
2835 + mtk_snand_read_fdm(snf, snf->page_cache + snf->writesize);
2837 + mtk_ecc_check_decode_error(snf);
2838 + mtk_snand_ecc_decoder_stop(snf);
2840 + ret = mtk_snand_check_ecc_result(snf, page);
2845 + dma_mem_unmap(snf->pdev, dma_addr, len, false);
2848 + nfi_write32(snf, NFI_CON, 0);
2849 + nfi_write16(snf, NFI_CNFG, 0);
2851 + /* Clear SNF done flag */
2852 + nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE);
2853 + nfi_write32(snf, SNF_STA_CTL1, 0);
2855 + /* Disable interrupt */
2856 + nfi_read32(snf, NFI_INTR_STA);
2857 + nfi_write32(snf, NFI_INTR_EN, 0);
2859 + nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN | LATCH_LAT, 0);
2864 +static void mtk_snand_from_raw_page(struct mtk_snand *snf, void *buf, void *oob)
2866 + uint32_t i, ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size;
2867 + uint8_t *eccptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size;
2868 + uint8_t *bufptr = buf, *oobptr = oob, *raw_sector;
2870 + for (i = 0; i < snf->ecc_steps; i++) {
2871 + raw_sector = snf->page_cache + i * snf->raw_sector_size;
2874 + memcpy(bufptr, raw_sector, snf->nfi_soc->sector_size);
2875 + bufptr += snf->nfi_soc->sector_size;
2878 + raw_sector += snf->nfi_soc->sector_size;
2881 + memcpy(oobptr, raw_sector, snf->nfi_soc->fdm_size);
2882 + oobptr += snf->nfi_soc->fdm_size;
2883 + raw_sector += snf->nfi_soc->fdm_size;
2885 + memcpy(eccptr, raw_sector, ecc_bytes);
2886 + eccptr += ecc_bytes;
2891 +static int mtk_snand_do_read_page(struct mtk_snand *snf, uint64_t addr,
2892 + void *buf, void *oob, bool raw, bool format)
2894 + uint64_t die_addr;
2895 + uint32_t page, dly_ctrl3;
2896 + int ret, retry_cnt = 0;
2898 + die_addr = mtk_snand_select_die_address(snf, addr);
2899 + page = die_addr >> snf->writesize_shift;
2901 + dly_ctrl3 = nfi_read32(snf, SNF_DLY_CTL3);
2903 + ret = mtk_snand_page_op(snf, page, SNAND_CMD_READ_TO_CACHE);
2907 + ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL);
2909 + snand_log_chip(snf->pdev, "Read to cache command timed out\n");
2914 + ret = mtk_snand_read_cache(snf, page, raw);
2915 + if (ret < 0 && ret != -EBADMSG)
2918 + if (ret == -EBADMSG && retry_cnt < 16) {
2919 + nfi_write32(snf, SNF_DLY_CTL3, retry_cnt * 2);
2925 + if(ret == -EBADMSG) {
2926 + nfi_write32(snf, SNF_DLY_CTL3, dly_ctrl3);
2927 + snand_log_chip(snf->pdev,
2928 + "NFI calibration failed. Original sample delay: 0x%x\n",
2931 + snand_log_chip(snf->pdev,
2932 + "NFI calibration passed. New sample delay: 0x%x\n",
2933 + nfi_read32(snf, SNF_DLY_CTL3));
2939 + mtk_snand_bm_swap_raw(snf);
2940 + mtk_snand_fdm_bm_swap_raw(snf);
2941 + mtk_snand_from_raw_page(snf, buf, oob);
2944 + memcpy(buf, snf->page_cache, snf->writesize);
2947 + memset(oob, 0xff, snf->oobsize);
2948 + memcpy(oob, snf->page_cache + snf->writesize,
2949 + snf->ecc_steps * snf->spare_per_sector);
2953 + mtk_snand_bm_swap(snf);
2954 + mtk_snand_fdm_bm_swap(snf);
2957 + memcpy(buf, snf->page_cache, snf->writesize);
2960 + memset(oob, 0xff, snf->oobsize);
2961 + memcpy(oob, snf->page_cache + snf->writesize,
2962 + snf->ecc_steps * snf->nfi_soc->fdm_size);
2969 +int mtk_snand_read_page(struct mtk_snand *snf, uint64_t addr, void *buf,
2970 + void *oob, bool raw)
2972 + if (!snf || (!buf && !oob))
2975 + if (addr >= snf->size)
2978 + return mtk_snand_do_read_page(snf, addr, buf, oob, raw, true);
2981 +static void mtk_snand_write_fdm(struct mtk_snand *snf, const uint8_t *buf)
2983 + uint32_t vall, valm, fdm_size = snf->nfi_soc->fdm_size;
2984 + const uint8_t *oobptr = buf;
2987 + for (i = 0; i < snf->ecc_steps; i++) {
2991 + for (j = 0; j < 8; j++) {
2993 + vall |= (j < fdm_size ? oobptr[j] : 0xff)
2996 + valm |= (j < fdm_size ? oobptr[j] : 0xff)
3000 + nfi_write32(snf, NFI_FDML(i), vall);
3001 + nfi_write32(snf, NFI_FDMM(i), valm);
3003 + oobptr += fdm_size;
3007 +static int mtk_snand_program_load(struct mtk_snand *snf, uint32_t page,
3010 + uint32_t coladdr, rwbytes, mode, len, val;
3011 + uintptr_t dma_addr;
3014 + /* Column address with plane bit */
3015 + coladdr = mtk_snand_get_plane_address(snf, page);
3017 + mtk_snand_mac_reset(snf);
3018 + mtk_nfi_reset(snf);
3020 + /* Write FDM registers if necessary */
3022 + mtk_snand_write_fdm(snf, snf->page_cache + snf->writesize);
3025 + nfi_write32(snf, SNF_PG_CTL1, (snf->opcode_pl << PG_LOAD_CMD_S));
3027 + /* Column address */
3028 + nfi_write32(snf, SNF_PG_CTL2, coladdr);
3030 + /* Set write mode */
3031 + mode = snf->mode_pl ? PG_LOAD_X4_EN : 0;
3032 + nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, mode | PG_LOAD_CUSTOM_EN);
3034 + /* Set bytes to write */
3035 + rwbytes = snf->ecc_steps * snf->raw_sector_size;
3036 + nfi_write32(snf, SNF_MISC_CTL2, (rwbytes << PROGRAM_LOAD_BYTE_NUM_S) |
3039 + /* NFI write prepare */
3040 + mode = raw ? 0 : CNFG_HW_ECC_EN | CNFG_AUTO_FMT_EN;
3041 + nfi_write16(snf, NFI_CNFG, (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) |
3042 + CNFG_DMA_BURST_EN | CNFG_DMA_MODE | mode);
3044 + nfi_write32(snf, NFI_CON, (snf->ecc_steps << CON_SEC_NUM_S));
3046 + /* Prepare for DMA write */
3047 + len = snf->writesize + snf->oobsize;
3048 + ret = dma_mem_map(snf->pdev, snf->page_cache, &dma_addr, len, true);
3050 + snand_log_nfi(snf->pdev,
3051 + "DMA map to device failed with %d\n", ret);
3055 + nfi_write32(snf, NFI_STRADDR, (uint32_t)dma_addr);
3058 + mtk_snand_ecc_encoder_start(snf);
3060 + /* Prepare for custom write interrupt */
3061 + nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG);
3062 + irq_completion_init(snf->pdev);
3064 + /* Trigger NFI into custom mode */
3065 + nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE);
3067 + /* Start DMA write */
3068 + nfi_rmw32(snf, NFI_CON, 0, CON_BWR);
3069 + nfi_write16(snf, NFI_STRDATA, STR_DATA);
3071 + /* Wait for operation finished */
3072 + ret = irq_completion_wait(snf->pdev, snf->nfi_base + SNF_STA_CTL1,
3073 + CUS_PG_DONE, SNFI_POLL_INTERVAL);
3075 + snand_log_nfi(snf->pdev,
3076 + "DMA timed out for program load\n");
3080 + /* Wait for NFI_SEC_CNTR returning expected value */
3081 + ret = read32_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val,
3082 + NFI_SEC_CNTR(val) >= snf->ecc_steps,
3083 + 0, SNFI_POLL_INTERVAL);
3085 + snand_log_nfi(snf->pdev,
3086 + "Timed out waiting for BUS_SEC_CNTR\n");
3091 + mtk_snand_ecc_encoder_stop(snf);
3095 + dma_mem_unmap(snf->pdev, dma_addr, len, true);
3098 + nfi_write32(snf, NFI_CON, 0);
3099 + nfi_write16(snf, NFI_CNFG, 0);
3101 + /* Clear SNF done flag */
3102 + nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE);
3103 + nfi_write32(snf, SNF_STA_CTL1, 0);
3105 + /* Disable interrupt */
3106 + nfi_read32(snf, NFI_INTR_STA);
3107 + nfi_write32(snf, NFI_INTR_EN, 0);
3109 + nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0);
3114 +static void mtk_snand_to_raw_page(struct mtk_snand *snf,
3115 + const void *buf, const void *oob,
3118 + uint32_t i, ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size;
3119 + const uint8_t *eccptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size;
3120 + const uint8_t *bufptr = buf, *oobptr = oob;
3121 + uint8_t *raw_sector;
3123 + memset(snf->page_cache, 0xff, snf->writesize + snf->oobsize);
3124 + for (i = 0; i < snf->ecc_steps; i++) {
3125 + raw_sector = snf->page_cache + i * snf->raw_sector_size;
3128 + memcpy(raw_sector, bufptr, snf->nfi_soc->sector_size);
3129 + bufptr += snf->nfi_soc->sector_size;
3132 + raw_sector += snf->nfi_soc->sector_size;
3135 + memcpy(raw_sector, oobptr, snf->nfi_soc->fdm_size);
3136 + oobptr += snf->nfi_soc->fdm_size;
3137 + raw_sector += snf->nfi_soc->fdm_size;
3140 + memset(raw_sector, 0xff, ecc_bytes);
3142 + memcpy(raw_sector, eccptr, ecc_bytes);
3143 + eccptr += ecc_bytes;
3148 +static bool mtk_snand_is_empty_page(struct mtk_snand *snf, const void *buf,
3151 + const uint8_t *p = buf;
3155 + for (i = 0; i < snf->writesize; i++) {
3162 + for (j = 0; j < snf->ecc_steps; j++) {
3163 + p = oob + j * snf->nfi_soc->fdm_size;
3165 + for (i = 0; i < snf->nfi_soc->fdm_ecc_size; i++) {
3175 +static int mtk_snand_do_write_page(struct mtk_snand *snf, uint64_t addr,
3176 + const void *buf, const void *oob,
3177 + bool raw, bool format)
3179 + uint64_t die_addr;
3180 + bool empty_ecc = false;
3184 + die_addr = mtk_snand_select_die_address(snf, addr);
3185 + page = die_addr >> snf->writesize_shift;
3187 + if (!raw && mtk_snand_is_empty_page(snf, buf, oob)) {
3189 + * If the data in the page to be ecc-ed is full 0xff,
3190 + * change to raw write mode
3195 + /* fill ecc parity code region with 0xff */
3201 + mtk_snand_to_raw_page(snf, buf, oob, empty_ecc);
3202 + mtk_snand_fdm_bm_swap_raw(snf);
3203 + mtk_snand_bm_swap_raw(snf);
3205 + memset(snf->page_cache, 0xff,
3206 + snf->writesize + snf->oobsize);
3209 + memcpy(snf->page_cache, buf, snf->writesize);
3212 + memcpy(snf->page_cache + snf->writesize, oob,
3213 + snf->ecc_steps * snf->spare_per_sector);
3217 + memset(snf->page_cache, 0xff, snf->writesize + snf->oobsize);
3219 + memcpy(snf->page_cache, buf, snf->writesize);
3222 + memcpy(snf->page_cache + snf->writesize, oob,
3223 + snf->ecc_steps * snf->nfi_soc->fdm_size);
3226 + mtk_snand_fdm_bm_swap(snf);
3227 + mtk_snand_bm_swap(snf);
3230 + ret = mtk_snand_write_enable(snf);
3234 + ret = mtk_snand_program_load(snf, page, raw);
3238 + ret = mtk_snand_page_op(snf, page, SNAND_CMD_PROGRAM_EXECUTE);
3242 + ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL);
3244 + snand_log_chip(snf->pdev,
3245 + "Page program command timed out on page %u\n",
3250 + if (ret & SNAND_STATUS_PROGRAM_FAIL) {
3251 + snand_log_chip(snf->pdev,
3252 + "Page program failed on page %u\n", page);
3259 +int mtk_snand_write_page(struct mtk_snand *snf, uint64_t addr, const void *buf,
3260 + const void *oob, bool raw)
3262 + if (!snf || (!buf && !oob))
3265 + if (addr >= snf->size)
3268 + return mtk_snand_do_write_page(snf, addr, buf, oob, raw, true);
3271 +int mtk_snand_erase_block(struct mtk_snand *snf, uint64_t addr)
3273 + uint64_t die_addr;
3274 + uint32_t page, block;
3280 + if (addr >= snf->size)
3283 + die_addr = mtk_snand_select_die_address(snf, addr);
3284 + block = die_addr >> snf->erasesize_shift;
3285 + page = block << (snf->erasesize_shift - snf->writesize_shift);
3287 + ret = mtk_snand_write_enable(snf);
3291 + ret = mtk_snand_page_op(snf, page, SNAND_CMD_BLOCK_ERASE);
3295 + ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL);
3297 + snand_log_chip(snf->pdev,
3298 + "Block erase command timed out on block %u\n",
3303 + if (ret & SNAND_STATUS_ERASE_FAIL) {
3304 + snand_log_chip(snf->pdev,
3305 + "Block erase failed on block %u\n", block);
3312 +static int mtk_snand_block_isbad_std(struct mtk_snand *snf, uint64_t addr)
3316 + ret = mtk_snand_do_read_page(snf, addr, NULL, snf->buf_cache, true,
3318 + if (ret && ret != -EBADMSG)
3321 + return snf->buf_cache[0] != 0xff;
3324 +static int mtk_snand_block_isbad_mtk(struct mtk_snand *snf, uint64_t addr)
3328 + ret = mtk_snand_do_read_page(snf, addr, NULL, snf->buf_cache, true,
3330 + if (ret && ret != -EBADMSG)
3333 + return snf->buf_cache[0] != 0xff;
3336 +int mtk_snand_block_isbad(struct mtk_snand *snf, uint64_t addr)
3341 + if (addr >= snf->size)
3344 + addr &= ~snf->erasesize_mask;
3346 + if (snf->nfi_soc->bbm_swap)
3347 + return mtk_snand_block_isbad_std(snf, addr);
3349 + return mtk_snand_block_isbad_mtk(snf, addr);
3352 +static int mtk_snand_block_markbad_std(struct mtk_snand *snf, uint64_t addr)
3354 + /* Standard BBM position */
3355 + memset(snf->buf_cache, 0xff, snf->oobsize);
3356 + snf->buf_cache[0] = 0;
3358 + return mtk_snand_do_write_page(snf, addr, NULL, snf->buf_cache, true,
3362 +static int mtk_snand_block_markbad_mtk(struct mtk_snand *snf, uint64_t addr)
3364 + /* Write the whole page with zeros */
3365 + memset(snf->buf_cache, 0, snf->writesize + snf->oobsize);
3367 + return mtk_snand_do_write_page(snf, addr, snf->buf_cache,
3368 + snf->buf_cache + snf->writesize, true,
3372 +int mtk_snand_block_markbad(struct mtk_snand *snf, uint64_t addr)
3377 + if (addr >= snf->size)
3380 + addr &= ~snf->erasesize_mask;
3382 + if (snf->nfi_soc->bbm_swap)
3383 + return mtk_snand_block_markbad_std(snf, addr);
3385 + return mtk_snand_block_markbad_mtk(snf, addr);
3388 +int mtk_snand_fill_oob(struct mtk_snand *snf, uint8_t *oobraw,
3389 + const uint8_t *oobbuf, size_t ooblen)
3391 + size_t len = ooblen, sect_fdm_len;
3392 + const uint8_t *oob = oobbuf;
3393 + uint32_t step = 0;
3395 + if (!snf || !oobraw || !oob)
3398 + while (len && step < snf->ecc_steps) {
3399 + sect_fdm_len = snf->nfi_soc->fdm_size - 1;
3400 + if (sect_fdm_len > len)
3401 + sect_fdm_len = len;
3403 + memcpy(oobraw + step * snf->nfi_soc->fdm_size + 1, oob,
3406 + len -= sect_fdm_len;
3407 + oob += sect_fdm_len;
3414 +int mtk_snand_transfer_oob(struct mtk_snand *snf, uint8_t *oobbuf,
3415 + size_t ooblen, const uint8_t *oobraw)
3417 + size_t len = ooblen, sect_fdm_len;
3418 + uint8_t *oob = oobbuf;
3419 + uint32_t step = 0;
3421 + if (!snf || !oobraw || !oob)
3424 + while (len && step < snf->ecc_steps) {
3425 + sect_fdm_len = snf->nfi_soc->fdm_size - 1;
3426 + if (sect_fdm_len > len)
3427 + sect_fdm_len = len;
3429 + memcpy(oob, oobraw + step * snf->nfi_soc->fdm_size + 1,
3432 + len -= sect_fdm_len;
3433 + oob += sect_fdm_len;
3440 +int mtk_snand_read_page_auto_oob(struct mtk_snand *snf, uint64_t addr,
3441 + void *buf, void *oob, size_t ooblen,
3442 + size_t *actualooblen, bool raw)
3444 + int ret, oobremain;
3450 + return mtk_snand_read_page(snf, addr, buf, NULL, raw);
3452 + ret = mtk_snand_read_page(snf, addr, buf, snf->buf_cache, raw);
3453 + if (ret && ret != -EBADMSG) {
3455 + *actualooblen = 0;
3459 + oobremain = mtk_snand_transfer_oob(snf, oob, ooblen, snf->buf_cache);
3461 + *actualooblen = ooblen - oobremain;
3466 +int mtk_snand_write_page_auto_oob(struct mtk_snand *snf, uint64_t addr,
3467 + const void *buf, const void *oob,
3468 + size_t ooblen, size_t *actualooblen, bool raw)
3476 + return mtk_snand_write_page(snf, addr, buf, NULL, raw);
3478 + memset(snf->buf_cache, 0xff, snf->oobsize);
3479 + oobremain = mtk_snand_fill_oob(snf, snf->buf_cache, oob, ooblen);
3481 + *actualooblen = ooblen - oobremain;
3483 + return mtk_snand_write_page(snf, addr, buf, snf->buf_cache, raw);
3486 +int mtk_snand_get_chip_info(struct mtk_snand *snf,
3487 + struct mtk_snand_chip_info *info)
3489 + if (!snf || !info)
3492 + info->model = snf->model;
3493 + info->chipsize = snf->size;
3494 + info->blocksize = snf->erasesize;
3495 + info->pagesize = snf->writesize;
3496 + info->sparesize = snf->oobsize;
3497 + info->spare_per_sector = snf->spare_per_sector;
3498 + info->fdm_size = snf->nfi_soc->fdm_size;
3499 + info->fdm_ecc_size = snf->nfi_soc->fdm_ecc_size;
3500 + info->num_sectors = snf->ecc_steps;
3501 + info->sector_size = snf->nfi_soc->sector_size;
3502 + info->ecc_strength = snf->ecc_strength;
3503 + info->ecc_bytes = snf->ecc_bytes;
3508 +int mtk_snand_irq_process(struct mtk_snand *snf)
3510 + uint32_t sta, ien;
3515 + sta = nfi_read32(snf, NFI_INTR_STA);
3516 + ien = nfi_read32(snf, NFI_INTR_EN);
3521 + nfi_write32(snf, NFI_INTR_EN, 0);
3522 + irq_completion_done(snf->pdev);
3527 +static int mtk_snand_select_spare_per_sector(struct mtk_snand *snf)
3529 + uint32_t spare_per_step = snf->oobsize / snf->ecc_steps;
3533 + * If we're using the 1KB sector size, HW will automatically
3534 + * double the spare size. So we should only use half of the value.
3536 + if (snf->nfi_soc->sector_size == 1024)
3539 + spare_per_step /= mul;
3541 + for (i = snf->nfi_soc->num_spare_size - 1; i >= 0; i--) {
3542 + if (snf->nfi_soc->spare_sizes[i] <= spare_per_step) {
3543 + snf->spare_per_sector = snf->nfi_soc->spare_sizes[i];
3544 + snf->spare_per_sector *= mul;
3549 + snand_log_nfi(snf->pdev,
3550 + "Page size %u+%u is not supported\n", snf->writesize,
3556 +static int mtk_snand_pagefmt_setup(struct mtk_snand *snf)
3558 + uint32_t spare_size_idx, spare_size_shift, pagesize_idx;
3559 + uint32_t sector_size_512;
3561 + if (snf->nfi_soc->sector_size == 512) {
3562 + sector_size_512 = NFI_SEC_SEL_512;
3563 + spare_size_shift = NFI_SPARE_SIZE_S;
3565 + sector_size_512 = 0;
3566 + spare_size_shift = NFI_SPARE_SIZE_LS_S;
3569 + switch (snf->writesize) {
3571 + pagesize_idx = NFI_PAGE_SIZE_512_2K;
3574 + if (snf->nfi_soc->sector_size == 512)
3575 + pagesize_idx = NFI_PAGE_SIZE_2K_4K;
3577 + pagesize_idx = NFI_PAGE_SIZE_512_2K;
3580 + if (snf->nfi_soc->sector_size == 512)
3581 + pagesize_idx = NFI_PAGE_SIZE_4K_8K;
3583 + pagesize_idx = NFI_PAGE_SIZE_2K_4K;
3586 + if (snf->nfi_soc->sector_size == 512)
3587 + pagesize_idx = NFI_PAGE_SIZE_8K_16K;
3589 + pagesize_idx = NFI_PAGE_SIZE_4K_8K;
3592 + pagesize_idx = NFI_PAGE_SIZE_8K_16K;
3595 + snand_log_nfi(snf->pdev, "Page size %u is not supported\n",
3600 + spare_size_idx = mtk_snand_select_spare_per_sector(snf);
3601 + if (unlikely(spare_size_idx < 0))
3604 + snf->raw_sector_size = snf->nfi_soc->sector_size +
3605 + snf->spare_per_sector;
3607 + /* Setup page format */
3608 + nfi_write32(snf, NFI_PAGEFMT,
3609 + (snf->nfi_soc->fdm_ecc_size << NFI_FDM_ECC_NUM_S) |
3610 + (snf->nfi_soc->fdm_size << NFI_FDM_NUM_S) |
3611 + (spare_size_idx << spare_size_shift) |
3612 + (pagesize_idx << NFI_PAGE_SIZE_S) |
3618 +static enum snand_flash_io mtk_snand_select_opcode(struct mtk_snand *snf,
3619 + uint32_t snfi_caps, uint8_t *opcode,
3621 + const struct snand_io_cap *op_cap)
3625 + caps = snfi_caps & op_cap->caps;
3629 + *opcode = op_cap->opcodes[i - 1].opcode;
3631 + *dummy = op_cap->opcodes[i - 1].dummy;
3635 + return __SNAND_IO_MAX;
3638 +static int mtk_snand_select_opcode_rfc(struct mtk_snand *snf,
3639 + uint32_t snfi_caps,
3640 + const struct snand_io_cap *op_cap)
3642 + enum snand_flash_io idx;
3644 + static const uint8_t rfc_modes[__SNAND_IO_MAX] = {
3645 + [SNAND_IO_1_1_1] = DATA_READ_MODE_X1,
3646 + [SNAND_IO_1_1_2] = DATA_READ_MODE_X2,
3647 + [SNAND_IO_1_2_2] = DATA_READ_MODE_DUAL,
3648 + [SNAND_IO_1_1_4] = DATA_READ_MODE_X4,
3649 + [SNAND_IO_1_4_4] = DATA_READ_MODE_QUAD,
3652 + idx = mtk_snand_select_opcode(snf, snfi_caps, &snf->opcode_rfc,
3653 + &snf->dummy_rfc, op_cap);
3654 + if (idx >= __SNAND_IO_MAX) {
3655 + snand_log_snfi(snf->pdev,
3656 + "No capable opcode for read from cache\n");
3660 + snf->mode_rfc = rfc_modes[idx];
3662 + if (idx == SNAND_IO_1_1_4 || idx == SNAND_IO_1_4_4)
3663 + snf->quad_spi_op = true;
3668 +static int mtk_snand_select_opcode_pl(struct mtk_snand *snf, uint32_t snfi_caps,
3669 + const struct snand_io_cap *op_cap)
3671 + enum snand_flash_io idx;
3673 + static const uint8_t pl_modes[__SNAND_IO_MAX] = {
3674 + [SNAND_IO_1_1_1] = 0,
3675 + [SNAND_IO_1_1_4] = 1,
3678 + idx = mtk_snand_select_opcode(snf, snfi_caps, &snf->opcode_pl,
3680 + if (idx >= __SNAND_IO_MAX) {
3681 + snand_log_snfi(snf->pdev,
3682 + "No capable opcode for program load\n");
3686 + snf->mode_pl = pl_modes[idx];
3688 + if (idx == SNAND_IO_1_1_4)
3689 + snf->quad_spi_op = true;
3694 +static int mtk_snand_setup(struct mtk_snand *snf,
3695 + const struct snand_flash_info *snand_info)
3697 + const struct snand_mem_org *memorg = &snand_info->memorg;
3698 + uint32_t i, msg_size, snfi_caps;
3701 + /* Calculate flash memory organization */
3702 + snf->model = snand_info->model;
3703 + snf->writesize = memorg->pagesize;
3704 + snf->oobsize = memorg->sparesize;
3705 + snf->erasesize = snf->writesize * memorg->pages_per_block;
3706 + snf->die_size = (uint64_t)snf->erasesize * memorg->blocks_per_die;
3707 + snf->size = snf->die_size * memorg->ndies;
3708 + snf->num_dies = memorg->ndies;
3710 + snf->writesize_mask = snf->writesize - 1;
3711 + snf->erasesize_mask = snf->erasesize - 1;
3712 + snf->die_mask = snf->die_size - 1;
3714 + snf->writesize_shift = ffs(snf->writesize) - 1;
3715 + snf->erasesize_shift = ffs(snf->erasesize) - 1;
3716 + snf->die_shift = mtk_snand_ffs64(snf->die_size) - 1;
3718 + snf->select_die = snand_info->select_die;
3720 + /* Determine opcodes for read from cache/program load */
3721 + snfi_caps = SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2;
3722 + if (snf->snfi_quad_spi)
3723 + snfi_caps |= SPI_IO_1_1_4 | SPI_IO_1_4_4;
3725 + ret = mtk_snand_select_opcode_rfc(snf, snfi_caps, snand_info->cap_rd);
3729 + ret = mtk_snand_select_opcode_pl(snf, snfi_caps, snand_info->cap_pl);
3733 + /* ECC and page format */
3734 + snf->ecc_steps = snf->writesize / snf->nfi_soc->sector_size;
3735 + if (snf->ecc_steps > snf->nfi_soc->max_sectors) {
3736 + snand_log_nfi(snf->pdev, "Page size %u is not supported\n",
3741 + ret = mtk_snand_pagefmt_setup(snf);
3745 + msg_size = snf->nfi_soc->sector_size + snf->nfi_soc->fdm_ecc_size;
3746 + ret = mtk_ecc_setup(snf, snf->nfi_base + NFI_FDM0L,
3747 + snf->spare_per_sector - snf->nfi_soc->fdm_size,
3752 + nfi_write16(snf, NFI_CNFG, 0);
3754 + /* Tuning options */
3755 + nfi_write16(snf, NFI_DEBUG_CON1, WBUF_EN);
3756 + nfi_write32(snf, SNF_DLY_CTL3, (snf->nfi_soc->sample_delay << SFCK_SAM_DLY_S));
3759 + nfi_read32(snf, NFI_INTR_STA);
3760 + nfi_write32(snf, NFI_INTR_EN, 0);
3762 + /* Clear SNF done flag */
3763 + nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE | CUS_PG_DONE);
3764 + nfi_write32(snf, SNF_STA_CTL1, 0);
3766 + /* Initialization on all dies */
3767 + for (i = 0; i < snf->num_dies; i++) {
3768 + mtk_snand_select_die(snf, i);
3770 + /* Disable On-Die ECC engine */
3771 + ret = mtk_snand_ondie_ecc_control(snf, false);
3775 + /* Disable block protection */
3776 + mtk_snand_unlock(snf);
3778 + /* Enable/disable quad-spi */
3779 + mtk_snand_qspi_control(snf, snf->quad_spi_op);
3782 + mtk_snand_select_die(snf, 0);
3787 +static int mtk_snand_id_probe(struct mtk_snand *snf,
3788 + const struct snand_flash_info **snand_info)
3790 + uint8_t id[4], op[2];
3793 + /* Read SPI-NAND JEDEC ID, OP + dummy/addr + ID */
3794 + op[0] = SNAND_CMD_READID;
3796 + ret = mtk_snand_mac_io(snf, op, 2, id, sizeof(id));
3800 + *snand_info = snand_flash_id_lookup(SNAND_ID_DYMMY, id);
3804 + /* Read SPI-NAND JEDEC ID, OP + ID */
3805 + op[0] = SNAND_CMD_READID;
3806 + ret = mtk_snand_mac_io(snf, op, 1, id, sizeof(id));
3810 + *snand_info = snand_flash_id_lookup(SNAND_ID_DYMMY, id);
3814 + snand_log_chip(snf->pdev,
3815 + "Unrecognized SPI-NAND ID: %02x %02x %02x %02x\n",
3816 + id[0], id[1], id[2], id[3]);
3821 +int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
3822 + struct mtk_snand **psnf)
3824 + const struct snand_flash_info *snand_info;
3825 + uint32_t rawpage_size, sect_bf_size;
3826 + struct mtk_snand tmpsnf, *snf;
3829 + if (!pdata || !psnf)
3832 + if (pdata->soc >= __SNAND_SOC_MAX) {
3833 + snand_log_chip(dev, "Invalid SOC %u for MTK-SNAND\n",
3838 + /* Dummy instance only for initial reset and id probe */
3839 + tmpsnf.nfi_base = pdata->nfi_base;
3840 + tmpsnf.ecc_base = pdata->ecc_base;
3841 + tmpsnf.soc = pdata->soc;
3842 + tmpsnf.nfi_soc = &mtk_snand_socs[pdata->soc];
3843 + tmpsnf.pdev = dev;
3845 + /* Switch to SNFI mode */
3846 + writel(SPI_MODE, tmpsnf.nfi_base + SNF_CFG);
3848 + /* Reset SNFI & NFI */
3849 + mtk_snand_mac_reset(&tmpsnf);
3850 + mtk_nfi_reset(&tmpsnf);
3852 + /* Reset SPI-NAND chip */
3853 + ret = mtk_snand_chip_reset(&tmpsnf);
3855 + snand_log_chip(dev, "Failed to reset SPI-NAND chip\n");
3859 + /* Probe SPI-NAND flash by JEDEC ID */
3860 + ret = mtk_snand_id_probe(&tmpsnf, &snand_info);
3864 + rawpage_size = snand_info->memorg.pagesize +
3865 + snand_info->memorg.sparesize;
3867 + sect_bf_size = mtk_snand_socs[pdata->soc].max_sectors *
3868 + sizeof(*snf->sect_bf);
3870 + /* Allocate memory for instance and cache */
3871 + snf = generic_mem_alloc(dev,
3872 + sizeof(*snf) + rawpage_size + sect_bf_size);
3874 + snand_log_chip(dev, "Failed to allocate memory for instance\n");
3878 + snf->sect_bf = (int *)((uintptr_t)snf + sizeof(*snf));
3879 + snf->buf_cache = (uint8_t *)((uintptr_t)snf->sect_bf + sect_bf_size);
3881 + /* Allocate memory for DMA buffer */
3882 + snf->page_cache = dma_mem_alloc(dev, rawpage_size);
3883 + if (!snf->page_cache) {
3884 + generic_mem_free(dev, snf);
3885 + snand_log_chip(dev,
3886 + "Failed to allocate memory for DMA buffer\n");
3890 + /* Fill up instance */
3892 + snf->nfi_base = pdata->nfi_base;
3893 + snf->ecc_base = pdata->ecc_base;
3894 + snf->soc = pdata->soc;
3895 + snf->nfi_soc = &mtk_snand_socs[pdata->soc];
3896 + snf->snfi_quad_spi = pdata->quad_spi;
3898 + /* Initialize SNFI & ECC engine */
3899 + ret = mtk_snand_setup(snf, snand_info);
3901 + dma_mem_free(dev, snf->page_cache);
3902 + generic_mem_free(dev, snf);
3911 +int mtk_snand_cleanup(struct mtk_snand *snf)
3916 + dma_mem_free(snf->pdev, snf->page_cache);
3917 + generic_mem_free(snf->pdev, snf);
3922 +++ b/drivers/mtd/mtk-snand/mtk-snand.h
3924 +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3926 + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
3928 + * Author: Weijie Gao <weijie.gao@mediatek.com>
3931 +#ifndef _MTK_SNAND_H_
3932 +#define _MTK_SNAND_H_
3934 +#ifndef PRIVATE_MTK_SNAND_HEADER
3935 +#include <stddef.h>
3936 +#include <stdint.h>
3937 +#include <stdbool.h>
3940 +enum mtk_snand_soc {
3948 +struct mtk_snand_platdata {
3951 + enum mtk_snand_soc soc;
3955 +struct mtk_snand_chip_info {
3956 + const char *model;
3957 + uint64_t chipsize;
3958 + uint32_t blocksize;
3959 + uint32_t pagesize;
3960 + uint32_t sparesize;
3961 + uint32_t spare_per_sector;
3962 + uint32_t fdm_size;
3963 + uint32_t fdm_ecc_size;
3964 + uint32_t num_sectors;
3965 + uint32_t sector_size;
3966 + uint32_t ecc_strength;
3967 + uint32_t ecc_bytes;
3971 +struct snand_flash_info;
3973 +int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
3974 + struct mtk_snand **psnf);
3975 +int mtk_snand_cleanup(struct mtk_snand *snf);
3977 +int mtk_snand_chip_reset(struct mtk_snand *snf);
3978 +int mtk_snand_read_page(struct mtk_snand *snf, uint64_t addr, void *buf,
3979 + void *oob, bool raw);
3980 +int mtk_snand_write_page(struct mtk_snand *snf, uint64_t addr, const void *buf,
3981 + const void *oob, bool raw);
3982 +int mtk_snand_erase_block(struct mtk_snand *snf, uint64_t addr);
3983 +int mtk_snand_block_isbad(struct mtk_snand *snf, uint64_t addr);
3984 +int mtk_snand_block_markbad(struct mtk_snand *snf, uint64_t addr);
3985 +int mtk_snand_fill_oob(struct mtk_snand *snf, uint8_t *oobraw,
3986 + const uint8_t *oobbuf, size_t ooblen);
3987 +int mtk_snand_transfer_oob(struct mtk_snand *snf, uint8_t *oobbuf,
3988 + size_t ooblen, const uint8_t *oobraw);
3989 +int mtk_snand_read_page_auto_oob(struct mtk_snand *snf, uint64_t addr,
3990 + void *buf, void *oob, size_t ooblen,
3991 + size_t *actualooblen, bool raw);
3992 +int mtk_snand_write_page_auto_oob(struct mtk_snand *snf, uint64_t addr,
3993 + const void *buf, const void *oob,
3994 + size_t ooblen, size_t *actualooblen,
3996 +int mtk_snand_get_chip_info(struct mtk_snand *snf,
3997 + struct mtk_snand_chip_info *info);
3998 +int mtk_snand_irq_process(struct mtk_snand *snf);
4000 +#endif /* _MTK_SNAND_H_ */