git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From cc52bfc04726a574fc4440bbbe0c710890e7040a Mon Sep 17 00:00:00 2001
   2 From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
   3 Date: Wed, 25 Jan 2023 21:40:22 +0530
   4 Subject: [PATCH] arm64: dts: rockchip: Enable Ethernet for Radxa CM3 IO
   5
   6 Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board.
   7
   8 Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
   9 Link: https://lore.kernel.org/r/20230125161023.12115-1-jagan@amarulasolutions.com
  10 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  11 ---
  12  .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++
  13  1 file changed, 93 insertions(+)
  14
  15 --- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
  16 +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
  17 @@ -21,6 +21,13 @@
  18                 stdout-path = "serial2:1500000n8";
  19         };
  20
  21 +       gmac1_clkin: external-gmac1-clock {
  22 +               compatible = "fixed-clock";
  23 +               clock-frequency = <125000000>;
  24 +               clock-output-names = "gmac1_clkin";
  25 +               #clock-cells = <0>;
  26 +       };
  27 +
  28         hdmi-con {
  29                 compatible = "hdmi-connector";
  30                 type = "a";
  31 @@ -83,6 +90,29 @@
  32         status = "okay";
  33  };
  34
  35 +&gmac1 {
  36 +       assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
  37 +       assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
  38 +       assigned-clock-rates = <0>, <125000000>;
  39 +       clock_in_out = "input";
  40 +       phy-handle = <&rgmii_phy1>;
  41 +       phy-mode = "rgmii";
  42 +       pinctrl-names = "default";
  43 +       pinctrl-0 = <&gmac1m0_miim
  44 +                    &gmac1m0_tx_bus2
  45 +                    &gmac1m0_rx_bus2
  46 +                    &gmac1m0_rgmii_clk
  47 +                    &gmac1m0_rgmii_bus
  48 +                    &gmac1m0_clkinout>;
  49 +       snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
  50 +       snps,reset-active-low;
  51 +       /* Reset time is 20ms, 100ms for rtl8211f */
  52 +       snps,reset-delays-us = <0 20000 100000>;
  53 +       tx_delay = <0x46>;
  54 +       rx_delay = <0x2e>;
  55 +       status = "okay";
  56 +};
  57 +
  58  &hdmi {
  59         avdd-0v9-supply = <&vdda0v9_image>;
  60         avdd-1v8-supply = <&vcca1v8_image>;
  61 @@ -105,7 +135,70 @@
  62         status = "okay";
  63  };
  64
  65 +&mdio1 {
  66 +       rgmii_phy1: ethernet-phy@0 {
  67 +               compatible="ethernet-phy-ieee802.3-c22";
  68 +               reg= <0x0>;
  69 +       };
  70 +};
  71 +
  72  &pinctrl {
  73 +       gmac1 {
  74 +               gmac1m0_miim: gmac1m0-miim {
  75 +                       rockchip,pins =
  76 +                               /* gmac1_mdcm0 */
  77 +                               <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
  78 +                               /* gmac1_mdiom0 */
  79 +                               <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
  80 +               };
  81 +
  82 +               gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
  83 +                       rockchip,pins =
  84 +                               /* gmac1_rxd0m0 */
  85 +                               <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
  86 +                               /* gmac1_rxd1m0 */
  87 +                               <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
  88 +                               /* gmac1_rxdvcrsm0 */
  89 +                               <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
  90 +               };
  91 +
  92 +               gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
  93 +                       rockchip,pins =
  94 +                               /* gmac1_txd0m0 */
  95 +                               <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
  96 +                               /* gmac1_txd1m0 */
  97 +                               <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
  98 +                               /* gmac1_txenm0 */
  99 +                               <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
 100 +               };
 101 +
 102 +               gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
 103 +                       rockchip,pins =
 104 +                               /* gmac1_rxclkm0 */
 105 +                               <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
 106 +                               /* gmac1_txclkm0 */
 107 +                               <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
 108 +               };
 109 +
 110 +               gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
 111 +                       rockchip,pins =
 112 +                               /* gmac1_rxd2m0 */
 113 +                               <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
 114 +                               /* gmac1_rxd3m0 */
 115 +                               <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
 116 +                               /* gmac1_txd2m0 */
 117 +                               <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
 118 +                               /* gmac1_txd3m0 */
 119 +                               <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
 120 +               };
 121 +
 122 +               gmac1m0_clkinout: gmac1m0-clkinout {
 123 +                       rockchip,pins =
 124 +                               /* gmac1_mclkinoutm0 */
 125 +                               <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
 126 +               };
 127 +       };
 128 +
 129         leds {
 130                 pi_nled_activity: pi-nled-activity {
 131                         rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;