git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 8ea673a8b30b4a32516b8adabb15e2a68ff02ec8 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Tue, 30 Nov 2021 18:29:04 +0100
   4 Subject: [PATCH] PCI: pci-bridge-emul: Add definitions for missing
   5  capabilities registers
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 pci-bridge-emul driver already allocates buffer for capabilities up to the
  11 PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
  12 registers. Add these missing definitions.
  13
  14 Link: https://lore.kernel.org/r/20211130172913.9727-3-kabel@kernel.org
  15 Signed-off-by: Pali Rohár <pali@kernel.org>
  16 Signed-off-by: Marek Behún <kabel@kernel.org>
  17 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  18 ---
  19  drivers/pci/pci-bridge-emul.c | 43 +++++++++++++++++++++++++++++++++++
  20  1 file changed, 43 insertions(+)
  21
  22 --- a/drivers/pci/pci-bridge-emul.c
  23 +++ b/drivers/pci/pci-bridge-emul.c
  24 @@ -251,6 +251,49 @@ struct pci_bridge_reg_behavior pcie_cap_
  25                 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
  26                 .w1c = PCI_EXP_RTSTA_PME,
  27         },
  28 +
  29 +       [PCI_EXP_DEVCAP2 / 4] = {
  30 +               /*
  31 +                * Device capabilities 2 register has reserved bits [30:27].
  32 +                * Also bits [26:24] are reserved for non-upstream ports.
  33 +                */
  34 +               .ro = BIT(31) | GENMASK(23, 0),
  35 +       },
  36 +
  37 +       [PCI_EXP_DEVCTL2 / 4] = {
  38 +               /*
  39 +                * Device control 2 register is RW. Bit 11 is reserved for
  40 +                * non-upstream ports.
  41 +                *
  42 +                * Device status 2 register is reserved.
  43 +                */
  44 +               .rw = GENMASK(15, 12) | GENMASK(10, 0),
  45 +       },
  46 +
  47 +       [PCI_EXP_LNKCAP2 / 4] = {
  48 +               /* Link capabilities 2 register has reserved bits [30:25] and 0. */
  49 +               .ro = BIT(31) | GENMASK(24, 1),
  50 +       },
  51 +
  52 +       [PCI_EXP_LNKCTL2 / 4] = {
  53 +               /*
  54 +                * Link control 2 register is RW.
  55 +                *
  56 +                * Link status 2 register has bits 5, 15 W1C;
  57 +                * bits 10, 11 reserved and others are RO.
  58 +                */
  59 +               .rw = GENMASK(15, 0),
  60 +               .w1c = (BIT(15) | BIT(5)) << 16,
  61 +               .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
  62 +       },
  63 +
  64 +       [PCI_EXP_SLTCAP2 / 4] = {
  65 +               /* Slot capabilities 2 register is reserved. */
  66 +       },
  67 +
  68 +       [PCI_EXP_SLTCTL2 / 4] = {
  69 +               /* Both Slot control 2 and Slot status 2 registers are reserved. */
  70 +       },
  71  };
  72
  73  /*