git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Sat, 5 Feb 2022 18:36:36 +0100
   3 Subject: [PATCH] arm64: dts: mediatek: mt7622: introduce nodes for
   4  Wireless Ethernet Dispatch
   5
   6 Introduce wed0 and wed1 nodes in order to enable offloading forwarding
   7 between ethernet and wireless devices on the mt7622 chipset.
   8
   9 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  10 ---
  11
  12 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  13 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  14 @@ -894,6 +894,11 @@
  15                 };
  16         };
  17
  18 +       hifsys: syscon@1af00000 {
  19 +               compatible = "mediatek,mt7622-hifsys", "syscon";
  20 +               reg = <0 0x1af00000 0 0x70>;
  21 +       };
  22 +
  23         ethsys: syscon@1b000000 {
  24                 compatible = "mediatek,mt7622-ethsys",
  25                              "syscon";
  26 @@ -912,6 +917,26 @@
  27                 #dma-cells = <1>;
  28         };
  29
  30 +       pcie_mirror: pcie-mirror@10000400 {
  31 +               compatible = "mediatek,mt7622-pcie-mirror",
  32 +                            "syscon";
  33 +               reg = <0 0x10000400 0 0x10>;
  34 +       };
  35 +
  36 +       wed0: wed@1020a000 {
  37 +               compatible = "mediatek,mt7622-wed",
  38 +                            "syscon";
  39 +               reg = <0 0x1020a000 0 0x1000>;
  40 +               interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
  41 +       };
  42 +
  43 +       wed1: wed@1020b000 {
  44 +               compatible = "mediatek,mt7622-wed",
  45 +                            "syscon";
  46 +               reg = <0 0x1020b000 0 0x1000>;
  47 +               interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
  48 +       };
  49 +
  50         eth: ethernet@1b100000 {
  51                 compatible = "mediatek,mt7622-eth",
  52                              "mediatek,mt2701-eth",
  53 @@ -939,6 +964,9 @@
  54                 mediatek,ethsys = <&ethsys>;
  55                 mediatek,sgmiisys = <&sgmiisys>;
  56                 mediatek,cci-control = <&cci_control2>;
  57 +               mediatek,wed = <&wed0>, <&wed1>;
  58 +               mediatek,pcie-mirror = <&pcie_mirror>;
  59 +               mediatek,hifsys = <&hifsys>;
  60                 dma-coherent;
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;