git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From 0fc57e4b5e39461fc0a54aae0afe4241363a7267 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Fri, 14 May 2021 23:00:03 +0200
   4 Subject: [PATCH] net: dsa: qca8k: add GLOBAL_FC settings needed for qca8327
   5
   6 Switch qca8327 needs special settings for the GLOBAL_FC_THRES regs.
   7
   8 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
   9 Signed-off-by: David S. Miller <davem@davemloft.net>
  10 ---
  11  drivers/net/dsa/qca8k.c | 10 ++++++++++
  12  drivers/net/dsa/qca8k.h |  6 ++++++
  13  2 files changed, 16 insertions(+)
  14
  15 --- a/drivers/net/dsa/qca8k.c
  16 +++ b/drivers/net/dsa/qca8k.c
  17 @@ -930,6 +930,16 @@ qca8k_setup(struct dsa_switch *ds)
  18                 }
  19         }
  20
  21 +       /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
  22 +       if (priv->switch_id == QCA8K_ID_QCA8327) {
  23 +               mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
  24 +                      QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
  25 +               qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
  26 +                         QCA8K_GLOBAL_FC_GOL_XON_THRES_S |
  27 +                         QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,
  28 +                         mask);
  29 +       }
  30 +
  31         /* Setup our port MTUs to match power on defaults */
  32         for (i = 0; i < QCA8K_NUM_PORTS; i++)
  33                 priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
  34 --- a/drivers/net/dsa/qca8k.h
  35 +++ b/drivers/net/dsa/qca8k.h
  36 @@ -168,6 +168,12 @@
  37  #define   QCA8K_PORT_LOOKUP_STATE                      GENMASK(18, 16)
  38  #define   QCA8K_PORT_LOOKUP_LEARN                      BIT(20)
  39
  40 +#define QCA8K_REG_GLOBAL_FC_THRESH                     0x800
  41 +#define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)             ((x) << 16)
  42 +#define   QCA8K_GLOBAL_FC_GOL_XON_THRES_S              GENMASK(24, 16)
  43 +#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)            ((x) << 0)
  44 +#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S             GENMASK(8, 0)
  45 +
  46  #define QCA8K_REG_PORT_HOL_CTRL0(_i)                   (0x970 + (_i) * 0x8)
  47  #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF             GENMASK(3, 0)
  48  #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)              ((x) << 0)