git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From be9165b9fdcf2a18ee201ffdaf8d69801387eb91 Mon Sep 17 00:00:00 2001
   2 From: Kuldeep Singh <kuldeep.singh@nxp.com>
   3 Date: Tue, 18 Feb 2020 10:42:50 +0800
   4 Subject: [PATCH] spi: spi-fsl-qspi: Introduce variable to fix different
   5  invalid master Id
   6
   7 Different platforms have different Master with different SourceID on
   8 AHB bus. The 0X0E Master ID is used by cluster 3 in case of LS2088A.
   9 So, patch introduce an invalid master id variable to fix invalid
  10 mastered on different platforms.
  11
  12 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
  13 Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
  14 [rebase]
  15 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  16 ---
  17  drivers/spi/spi-fsl-qspi.c | 17 +++++++++++++++++
  18  1 file changed, 17 insertions(+)
  19
  20 --- a/drivers/spi/spi-fsl-qspi.c
  21 +++ b/drivers/spi/spi-fsl-qspi.c
  22 @@ -68,6 +68,11 @@
  23  #define QUADSPI_FLSHCR_TCSH_MASK       GENMASK(11, 8)
  24  #define QUADSPI_FLSHCR_TDH_MASK                GENMASK(17, 16)
  25
  26 +#define QUADSPI_BUF0CR                  0x10
  27 +#define QUADSPI_BUF1CR                  0x14
  28 +#define QUADSPI_BUF2CR                  0x18
  29 +#define QUADSPI_BUFXCR_INVALID_MSTRID   0xe
  30 +
  31  #define QUADSPI_BUF3CR                 0x1c
  32  #define QUADSPI_BUF3CR_ALLMST_MASK     BIT(31)
  33  #define QUADSPI_BUF3CR_ADATSZ(x)       ((x) << 8)
  34 @@ -197,6 +202,7 @@
  35  struct fsl_qspi_devtype_data {
  36         unsigned int rxfifo;
  37         unsigned int txfifo;
  38 +       int invalid_mstrid;
  39         unsigned int ahb_buf_size;
  40         unsigned int quirks;
  41         bool little_endian;
  42 @@ -205,6 +211,7 @@ struct fsl_qspi_devtype_data {
  43  static const struct fsl_qspi_devtype_data vybrid_data = {
  44         .rxfifo = SZ_128,
  45         .txfifo = SZ_64,
  46 +       .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  47         .ahb_buf_size = SZ_1K,
  48         .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
  49         .little_endian = true,
  50 @@ -213,6 +220,7 @@ static const struct fsl_qspi_devtype_dat
  51  static const struct fsl_qspi_devtype_data imx6sx_data = {
  52         .rxfifo = SZ_128,
  53         .txfifo = SZ_512,
  54 +       .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  55         .ahb_buf_size = SZ_1K,
  56         .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
  57         .little_endian = true,
  58 @@ -221,6 +229,7 @@ static const struct fsl_qspi_devtype_dat
  59  static const struct fsl_qspi_devtype_data imx7d_data = {
  60         .rxfifo = SZ_128,
  61         .txfifo = SZ_512,
  62 +       .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  63         .ahb_buf_size = SZ_1K,
  64         .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  65                   QUADSPI_QUIRK_USE_TDH_SETTING,
  66 @@ -230,6 +239,7 @@ static const struct fsl_qspi_devtype_dat
  67  static const struct fsl_qspi_devtype_data imx6ul_data = {
  68         .rxfifo = SZ_128,
  69         .txfifo = SZ_512,
  70 +       .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  71         .ahb_buf_size = SZ_1K,
  72         .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
  73                   QUADSPI_QUIRK_USE_TDH_SETTING,
  74 @@ -239,6 +249,7 @@ static const struct fsl_qspi_devtype_dat
  75  static const struct fsl_qspi_devtype_data ls1021a_data = {
  76         .rxfifo = SZ_128,
  77         .txfifo = SZ_64,
  78 +       .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
  79         .ahb_buf_size = SZ_1K,
  80         .quirks = 0,
  81         .little_endian = false,
  82 @@ -248,6 +259,7 @@ static const struct fsl_qspi_devtype_dat
  83         .rxfifo = SZ_128,
  84         .txfifo = SZ_64,
  85         .ahb_buf_size = SZ_1K,
  86 +       .invalid_mstrid = 0x0,
  87         .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
  88         .little_endian = true,
  89  };
  90 @@ -661,6 +673,7 @@ static int fsl_qspi_exec_op(struct spi_m
  91         void __iomem *base = q->iobase;
  92         u32 addr_offset = 0;
  93         int err = 0;
  94 +       int invalid_mstrid = q->devtype_data->invalid_mstrid;
  95
  96         mutex_lock(&q->lock);
  97
  98 @@ -684,6 +697,10 @@ static int fsl_qspi_exec_op(struct spi_m
  99         qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
 100                     base + QUADSPI_SPTRCLR);
 101
 102 +       qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
 103 +       qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
 104 +       qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
 105 +
 106         fsl_qspi_prepare_lut(q, op);
 107
 108         /*