projects / openwrt / staging / svanheule.git / blob
? search:


2ae3734e4096658ad4a89eb6b71831d977329246
[openwrt/staging/svanheule.git] /
1 From 325fadf27b21f7d79843c3cc282b7f3e6620ad3d Mon Sep 17 00:00:00 2001
2 From: Balsam CHIHI <bchihi@baylibre.com>
3 Date: Thu, 9 Feb 2023 11:56:26 +0100
4 Subject: [PATCH 06/42] thermal/drivers/mediatek: Add the Low Voltage Thermal
5 Sensor driver
6
7 The Low Voltage Thermal Sensor (LVTS) is a multiple sensors, multi
8 controllers contained in a thermal domain.
9
10 A thermal domains can be the MCU or the AP.
11
12 Each thermal domains contain up to seven controllers, each thermal
13 controller handle up to four thermal sensors.
14
15 The LVTS has two Finite State Machines (FSM), one to handle the
16 functionin temperatures range like hot or cold temperature and another
17 one to handle monitoring trip point. The FSM notifies via interrupts
18 when a trip point is crossed.
19
20 The interrupt is managed at the thermal controller level, so when an
21 interrupt occurs, the driver has to find out which sensor triggered
22 such an interrupt.
23
24 The sampling of the thermal can be filtered or immediate. For the
25 former, the LVTS measures several points and applies a low pass
26 filter.
27
28 Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
29 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
30
31 On MT8195 Tomato Chromebook:
32
33 Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
34 Link: https://lore.kernel.org/r/20230209105628.50294-5-bchihi@baylibre.com
35 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
36 Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
37 ---
38 drivers/thermal/mediatek/Kconfig | 16 +
39 drivers/thermal/mediatek/Makefile | 1 +
40 drivers/thermal/mediatek/lvts_thermal.c | 1224 +++++++++++++++++++++++
41 3 files changed, 1241 insertions(+)
42 create mode 100644 drivers/thermal/mediatek/lvts_thermal.c
43
44 --- a/drivers/thermal/mediatek/Kconfig
45 +++ b/drivers/thermal/mediatek/Kconfig
46 @@ -18,4 +18,20 @@ config MTK_SOC_THERMAL
47 This driver configures thermal controllers to collect
48 temperature via AUXADC interface.
49
50 +config MTK_LVTS_THERMAL
51 + tristate "LVTS Thermal Driver for MediaTek SoCs"
52 + depends on HAS_IOMEM
53 + help
54 + Enable this option if you want to get SoC temperature
55 + information for supported MediaTek platforms.
56 + This driver configures LVTS (Low Voltage Thermal Sensor)
57 + thermal controllers to collect temperatures via ASIF
58 + (Analog Serial Interface).
59 +
60 +config MTK_LVTS_THERMAL_DEBUGFS
61 + bool "LVTS thermal debugfs"
62 + depends on MTK_LVTS_THERMAL && DEBUG_FS
63 + help
64 + Enable this option to debug the internals of the device driver.
65 +
66 endif
67 --- a/drivers/thermal/mediatek/Makefile
68 +++ b/drivers/thermal/mediatek/Makefile
69 @@ -1 +1,2 @@
70 obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o
71 +obj-$(CONFIG_MTK_LVTS_THERMAL) += lvts_thermal.o
72 --- /dev/null
73 +++ b/drivers/thermal/mediatek/lvts_thermal.c
74 @@ -0,0 +1,1224 @@
75 +// SPDX-License-Identifier: GPL-2.0-only
76 +/*
77 + * Copyright (c) 2023 MediaTek Inc.
78 + * Author: Balsam CHIHI <bchihi@baylibre.com>
79 + */
80 +
81 +#include <linux/clk.h>
82 +#include <linux/clk-provider.h>
83 +#include <linux/delay.h>
84 +#include <linux/debugfs.h>
85 +#include <linux/init.h>
86 +#include <linux/interrupt.h>
87 +#include <linux/iopoll.h>
88 +#include <linux/kernel.h>
89 +#include <linux/nvmem-consumer.h>
90 +#include <linux/of_device.h>
91 +#include <linux/platform_device.h>
92 +#include <linux/reset.h>
93 +#include <linux/thermal.h>
94 +#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
95 +
96 +#define LVTS_MONCTL0(__base) (__base + 0x0000)
97 +#define LVTS_MONCTL1(__base) (__base + 0x0004)
98 +#define LVTS_MONCTL2(__base) (__base + 0x0008)
99 +#define LVTS_MONINT(__base) (__base + 0x000C)
100 +#define LVTS_MONINTSTS(__base) (__base + 0x0010)
101 +#define LVTS_MONIDET0(__base) (__base + 0x0014)
102 +#define LVTS_MONIDET1(__base) (__base + 0x0018)
103 +#define LVTS_MONIDET2(__base) (__base + 0x001C)
104 +#define LVTS_MONIDET3(__base) (__base + 0x0020)
105 +#define LVTS_H2NTHRE(__base) (__base + 0x0024)
106 +#define LVTS_HTHRE(__base) (__base + 0x0028)
107 +#define LVTS_OFFSETH(__base) (__base + 0x0030)
108 +#define LVTS_OFFSETL(__base) (__base + 0x0034)
109 +#define LVTS_MSRCTL0(__base) (__base + 0x0038)
110 +#define LVTS_MSRCTL1(__base) (__base + 0x003C)
111 +#define LVTS_TSSEL(__base) (__base + 0x0040)
112 +#define LVTS_CALSCALE(__base) (__base + 0x0048)
113 +#define LVTS_ID(__base) (__base + 0x004C)
114 +#define LVTS_CONFIG(__base) (__base + 0x0050)
115 +#define LVTS_EDATA00(__base) (__base + 0x0054)
116 +#define LVTS_EDATA01(__base) (__base + 0x0058)
117 +#define LVTS_EDATA02(__base) (__base + 0x005C)
118 +#define LVTS_EDATA03(__base) (__base + 0x0060)
119 +#define LVTS_MSR0(__base) (__base + 0x0090)
120 +#define LVTS_MSR1(__base) (__base + 0x0094)
121 +#define LVTS_MSR2(__base) (__base + 0x0098)
122 +#define LVTS_MSR3(__base) (__base + 0x009C)
123 +#define LVTS_IMMD0(__base) (__base + 0x00A0)
124 +#define LVTS_IMMD1(__base) (__base + 0x00A4)
125 +#define LVTS_IMMD2(__base) (__base + 0x00A8)
126 +#define LVTS_IMMD3(__base) (__base + 0x00AC)
127 +#define LVTS_PROTCTL(__base) (__base + 0x00C0)
128 +#define LVTS_PROTTA(__base) (__base + 0x00C4)
129 +#define LVTS_PROTTB(__base) (__base + 0x00C8)
130 +#define LVTS_PROTTC(__base) (__base + 0x00CC)
131 +#define LVTS_CLKEN(__base) (__base + 0x00E4)
132 +
133 +#define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38))
134 +#define LVTS_GROUP_INTERVAL 1
135 +#define LVTS_FILTER_INTERVAL 1
136 +#define LVTS_SENSOR_INTERVAL 1
137 +#define LVTS_HW_FILTER 0x2
138 +#define LVTS_TSSEL_CONF 0x13121110
139 +#define LVTS_CALSCALE_CONF 0x300
140 +#define LVTS_MONINT_CONF 0x9FBF7BDE
141 +
142 +#define LVTS_INT_SENSOR0 0x0009001F
143 +#define LVTS_INT_SENSOR1 0X000881F0
144 +#define LVTS_INT_SENSOR2 0x00247C00
145 +#define LVTS_INT_SENSOR3 0x1FC00000
146 +
147 +#define LVTS_SENSOR_MAX 4
148 +#define LVTS_GOLDEN_TEMP_MAX 62
149 +#define LVTS_GOLDEN_TEMP_DEFAULT 50
150 +#define LVTS_COEFF_A -250460
151 +#define LVTS_COEFF_B 250460
152 +
153 +#define LVTS_MSR_IMMEDIATE_MODE 0
154 +#define LVTS_MSR_FILTERED_MODE 1
155 +
156 +#define LVTS_HW_SHUTDOWN_MT8195 105000
157 +
158 +static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
159 +static int coeff_b = LVTS_COEFF_B;
160 +
161 +struct lvts_sensor_data {
162 + int dt_id;
163 +};
164 +
165 +struct lvts_ctrl_data {
166 + struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
167 + int cal_offset[LVTS_SENSOR_MAX];
168 + int hw_tshut_temp;
169 + int num_lvts_sensor;
170 + int offset;
171 + int mode;
172 +};
173 +
174 +struct lvts_data {
175 + const struct lvts_ctrl_data *lvts_ctrl;
176 + int num_lvts_ctrl;
177 +};
178 +
179 +struct lvts_sensor {
180 + struct thermal_zone_device *tz;
181 + void __iomem *msr;
182 + void __iomem *base;
183 + int id;
184 + int dt_id;
185 +};
186 +
187 +struct lvts_ctrl {
188 + struct lvts_sensor sensors[LVTS_SENSOR_MAX];
189 + u32 calibration[LVTS_SENSOR_MAX];
190 + u32 hw_tshut_raw_temp;
191 + int num_lvts_sensor;
192 + int mode;
193 + void __iomem *base;
194 +};
195 +
196 +struct lvts_domain {
197 + struct lvts_ctrl *lvts_ctrl;
198 + struct reset_control *reset;
199 + struct clk *clk;
200 + int num_lvts_ctrl;
201 + void __iomem *base;
202 + size_t calib_len;
203 + u8 *calib;
204 +#ifdef CONFIG_DEBUG_FS
205 + struct dentry *dom_dentry;
206 +#endif
207 +};
208 +
209 +#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
210 +
211 +#define LVTS_DEBUG_FS_REGS(__reg) \
212 +{ \
213 + .name = __stringify(__reg), \
214 + .offset = __reg(0), \
215 +}
216 +
217 +static const struct debugfs_reg32 lvts_regs[] = {
218 + LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
219 + LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
220 + LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
221 + LVTS_DEBUG_FS_REGS(LVTS_MONINT),
222 + LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
223 + LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
224 + LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
225 + LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
226 + LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
227 + LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
228 + LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
229 + LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
230 + LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
231 + LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
232 + LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
233 + LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
234 + LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
235 + LVTS_DEBUG_FS_REGS(LVTS_ID),
236 + LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
237 + LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
238 + LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
239 + LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
240 + LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
241 + LVTS_DEBUG_FS_REGS(LVTS_MSR0),
242 + LVTS_DEBUG_FS_REGS(LVTS_MSR1),
243 + LVTS_DEBUG_FS_REGS(LVTS_MSR2),
244 + LVTS_DEBUG_FS_REGS(LVTS_MSR3),
245 + LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
246 + LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
247 + LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
248 + LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
249 + LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
250 + LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
251 + LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
252 + LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
253 + LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
254 +};
255 +
256 +static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
257 +{
258 + struct debugfs_regset32 *regset;
259 + struct lvts_ctrl *lvts_ctrl;
260 + struct dentry *dentry;
261 + char name[64];
262 + int i;
263 +
264 + lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
265 + if (!lvts_td->dom_dentry)
266 + return 0;
267 +
268 + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
269 +
270 + lvts_ctrl = &lvts_td->lvts_ctrl[i];
271 +
272 + sprintf(name, "controller%d", i);
273 + dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
274 + if (!dentry)
275 + continue;
276 +
277 + regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
278 + if (!regset)
279 + continue;
280 +
281 + regset->base = lvts_ctrl->base;
282 + regset->regs = lvts_regs;
283 + regset->nregs = ARRAY_SIZE(lvts_regs);
284 +
285 + debugfs_create_regset32("registers", 0400, dentry, regset);
286 + }
287 +
288 + return 0;
289 +}
290 +
291 +static void lvts_debugfs_exit(struct lvts_domain *lvts_td)
292 +{
293 + debugfs_remove_recursive(lvts_td->dom_dentry);
294 +}
295 +
296 +#else
297 +
298 +static inline int lvts_debugfs_init(struct device *dev,
299 + struct lvts_domain *lvts_td)
300 +{
301 + return 0;
302 +}
303 +
304 +static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
305 +
306 +#endif
307 +
308 +static int lvts_raw_to_temp(u32 raw_temp)
309 +{
310 + int temperature;
311 +
312 + temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
313 + temperature += coeff_b;
314 +
315 + return temperature;
316 +}
317 +
318 +static u32 lvts_temp_to_raw(int temperature)
319 +{
320 + u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
321 +
322 + raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
323 +
324 + return raw_temp;
325 +}
326 +
327 +static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
328 +{
329 + struct lvts_sensor *lvts_sensor = tz->devdata;
330 + void __iomem *msr = lvts_sensor->msr;
331 + u32 value;
332 +
333 + /*
334 + * Measurement registers:
335 + *
336 + * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
337 + *
338 + * Bits:
339 + *
340 + * 32-17: Unused
341 + * 16 : Valid temperature
342 + * 15-0 : Raw temperature
343 + */
344 + value = readl(msr);
345 +
346 + /*
347 + * As the thermal zone temperature will read before the
348 + * hardware sensor is fully initialized, we have to check the
349 + * validity of the temperature returned when reading the
350 + * measurement register. The thermal controller will set the
351 + * valid bit temperature only when it is totally initialized.
352 + *
353 + * Otherwise, we may end up with garbage values out of the
354 + * functionning temperature and directly jump to a system
355 + * shutdown.
356 + */
357 + if (!(value & BIT(16)))
358 + return -EAGAIN;
359 +
360 + *temp = lvts_raw_to_temp(value & 0xFFFF);
361 +
362 + return 0;
363 +}
364 +
365 +static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
366 +{
367 + struct lvts_sensor *lvts_sensor = tz->devdata;
368 + void __iomem *base = lvts_sensor->base;
369 + u32 raw_low = lvts_temp_to_raw(low);
370 + u32 raw_high = lvts_temp_to_raw(high);
371 +
372 + /*
373 + * Hot to normal temperature threshold
374 + *
375 + * LVTS_H2NTHRE
376 + *
377 + * Bits:
378 + *
379 + * 14-0 : Raw temperature for threshold
380 + */
381 + if (low != -INT_MAX) {
382 + dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low);
383 + writel(raw_low, LVTS_H2NTHRE(base));
384 + }
385 +
386 + /*
387 + * Hot temperature threshold
388 + *
389 + * LVTS_HTHRE
390 + *
391 + * Bits:
392 + *
393 + * 14-0 : Raw temperature for threshold
394 + */
395 + dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high);
396 + writel(raw_high, LVTS_HTHRE(base));
397 +
398 + return 0;
399 +}
400 +
401 +static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
402 +{
403 + irqreturn_t iret = IRQ_NONE;
404 + u32 value;
405 + u32 masks[] = {
406 + LVTS_INT_SENSOR0,
407 + LVTS_INT_SENSOR1,
408 + LVTS_INT_SENSOR2,
409 + LVTS_INT_SENSOR3
410 + };
411 + int i;
412 +
413 + /*
414 + * Interrupt monitoring status
415 + *
416 + * LVTS_MONINTST
417 + *
418 + * Bits:
419 + *
420 + * 31 : Interrupt for stage 3
421 + * 30 : Interrupt for stage 2
422 + * 29 : Interrupt for state 1
423 + * 28 : Interrupt using filter on sensor 3
424 + *
425 + * 27 : Interrupt using immediate on sensor 3
426 + * 26 : Interrupt normal to hot on sensor 3
427 + * 25 : Interrupt high offset on sensor 3
428 + * 24 : Interrupt low offset on sensor 3
429 + *
430 + * 23 : Interrupt hot threshold on sensor 3
431 + * 22 : Interrupt cold threshold on sensor 3
432 + * 21 : Interrupt using filter on sensor 2
433 + * 20 : Interrupt using filter on sensor 1
434 + *
435 + * 19 : Interrupt using filter on sensor 0
436 + * 18 : Interrupt using immediate on sensor 2
437 + * 17 : Interrupt using immediate on sensor 1
438 + * 16 : Interrupt using immediate on sensor 0
439 + *
440 + * 15 : Interrupt device access timeout interrupt
441 + * 14 : Interrupt normal to hot on sensor 2
442 + * 13 : Interrupt high offset interrupt on sensor 2
443 + * 12 : Interrupt low offset interrupt on sensor 2
444 + *
445 + * 11 : Interrupt hot threshold on sensor 2
446 + * 10 : Interrupt cold threshold on sensor 2
447 + * 9 : Interrupt normal to hot on sensor 1
448 + * 8 : Interrupt high offset interrupt on sensor 1
449 + *
450 + * 7 : Interrupt low offset interrupt on sensor 1
451 + * 6 : Interrupt hot threshold on sensor 1
452 + * 5 : Interrupt cold threshold on sensor 1
453 + * 4 : Interrupt normal to hot on sensor 0
454 + *
455 + * 3 : Interrupt high offset interrupt on sensor 0
456 + * 2 : Interrupt low offset interrupt on sensor 0
457 + * 1 : Interrupt hot threshold on sensor 0
458 + * 0 : Interrupt cold threshold on sensor 0
459 + *
460 + * We are interested in the sensor(s) responsible of the
461 + * interrupt event. We update the thermal framework with the
462 + * thermal zone associated with the sensor. The framework will
463 + * take care of the rest whatever the kind of interrupt, we
464 + * are only interested in which sensor raised the interrupt.
465 + *
466 + * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
467 + * => 0x1FC00000
468 + * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
469 + * => 0x00247C00
470 + * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000
471 + * => 0X000881F0
472 + * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
473 + * => 0x0009001F
474 + */
475 + value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
476 +
477 + /*
478 + * Let's figure out which sensors raised the interrupt
479 + *
480 + * NOTE: the masks array must be ordered with the index
481 + * corresponding to the sensor id eg. index=0, mask for
482 + * sensor0.
483 + */
484 + for (i = 0; i < ARRAY_SIZE(masks); i++) {
485 +
486 + if (!(value & masks[i]))
487 + continue;
488 +
489 + thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
490 + THERMAL_TRIP_VIOLATED);
491 + iret = IRQ_HANDLED;
492 + }
493 +
494 + /*
495 + * Write back to clear the interrupt status (W1C)
496 + */
497 + writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
498 +
499 + return iret;
500 +}
501 +
502 +/*
503 + * Temperature interrupt handler. Even if the driver supports more
504 + * interrupt modes, we use the interrupt when the temperature crosses
505 + * the hot threshold the way up and the way down (modulo the
506 + * hysteresis).
507 + *
508 + * Each thermal domain has a couple of interrupts, one for hardware
509 + * reset and another one for all the thermal events happening on the
510 + * different sensors.
511 + *
512 + * The interrupt is configured for thermal events when crossing the
513 + * hot temperature limit. At each interrupt, we check in every
514 + * controller if there is an interrupt pending.
515 + */
516 +static irqreturn_t lvts_irq_handler(int irq, void *data)
517 +{
518 + struct lvts_domain *lvts_td = data;
519 + irqreturn_t aux, iret = IRQ_NONE;
520 + int i;
521 +
522 + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
523 +
524 + aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl);
525 + if (aux != IRQ_HANDLED)
526 + continue;
527 +
528 + iret = IRQ_HANDLED;
529 + }
530 +
531 + return iret;
532 +}
533 +
534 +static struct thermal_zone_device_ops lvts_ops = {
535 + .get_temp = lvts_get_temp,
536 + .set_trips = lvts_set_trips,
537 +};
538 +
539 +static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
540 + const struct lvts_ctrl_data *lvts_ctrl_data)
541 +{
542 + struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
543 + void __iomem *msr_regs[] = {
544 + LVTS_MSR0(lvts_ctrl->base),
545 + LVTS_MSR1(lvts_ctrl->base),
546 + LVTS_MSR2(lvts_ctrl->base),
547 + LVTS_MSR3(lvts_ctrl->base)
548 + };
549 +
550 + void __iomem *imm_regs[] = {
551 + LVTS_IMMD0(lvts_ctrl->base),
552 + LVTS_IMMD1(lvts_ctrl->base),
553 + LVTS_IMMD2(lvts_ctrl->base),
554 + LVTS_IMMD3(lvts_ctrl->base)
555 + };
556 +
557 + int i;
558 +
559 + for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) {
560 +
561 + int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
562 +
563 + /*
564 + * At this point, we don't know which id matches which
565 + * sensor. Let's set arbitrally the id from the index.
566 + */
567 + lvts_sensor[i].id = i;
568 +
569 + /*
570 + * The thermal zone registration will set the trip
571 + * point interrupt in the thermal controller
572 + * register. But this one will be reset in the
573 + * initialization after. So we need to post pone the
574 + * thermal zone creation after the controller is
575 + * setup. For this reason, we store the device tree
576 + * node id from the data in the sensor structure
577 + */
578 + lvts_sensor[i].dt_id = dt_id;
579 +
580 + /*
581 + * We assign the base address of the thermal
582 + * controller as a back pointer. So it will be
583 + * accessible from the different thermal framework ops
584 + * as we pass the lvts_sensor pointer as thermal zone
585 + * private data.
586 + */
587 + lvts_sensor[i].base = lvts_ctrl->base;
588 +
589 + /*
590 + * Each sensor has its own register address to read from.
591 + */
592 + lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
593 + imm_regs[i] : msr_regs[i];
594 + };
595 +
596 + lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
597 +
598 + return 0;
599 +}
600 +
601 +/*
602 + * The efuse blob values follows the sensor enumeration per thermal
603 + * controller. The decoding of the stream is as follow:
604 + *
605 + * <--?-> <----big0 ???---> <-sensor0-> <-0->
606 + * ------------------------------------------
607 + * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
608 + * ------------------------------------------
609 + *
610 + * <--sensor1--><-0-> <----big1 ???---> <-sen
611 + * ------------------------------------------
612 + * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
613 + * ------------------------------------------
614 + *
615 + * sor0-> <-0-> <-sensor1-> <-0-> ..........
616 + * ------------------------------------------
617 + * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
618 + * ------------------------------------------
619 + *
620 + * And so on ...
621 + *
622 + * The data description gives the offset of the calibration data in
623 + * this bytes stream for each sensor.
624 + *
625 + * Each thermal controller can handle up to 4 sensors max, we don't
626 + * care if there are less as the array of calibration is sized to 4
627 + * anyway. The unused sensor slot will be zeroed.
628 + */
629 +static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
630 + const struct lvts_ctrl_data *lvts_ctrl_data,
631 + u8 *efuse_calibration)
632 +{
633 + int i;
634 +
635 + for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++)
636 + memcpy(&lvts_ctrl->calibration[i],
637 + efuse_calibration + lvts_ctrl_data->cal_offset[i], 2);
638 +
639 + return 0;
640 +}
641 +
642 +/*
643 + * The efuse bytes stream can be split into different chunk of
644 + * nvmems. This function reads and concatenate those into a single
645 + * buffer so it can be read sequentially when initializing the
646 + * calibration data.
647 + */
648 +static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
649 + const struct lvts_data *lvts_data)
650 +{
651 + struct device_node *np = dev_of_node(dev);
652 + struct nvmem_cell *cell;
653 + struct property *prop;
654 + const char *cell_name;
655 +
656 + of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
657 + size_t len;
658 + u8 *efuse;
659 +
660 + cell = of_nvmem_cell_get(np, cell_name);
661 + if (IS_ERR(cell)) {
662 + dev_err(dev, "Failed to get cell '%s'\n", cell_name);
663 + return PTR_ERR(cell);
664 + }
665 +
666 + efuse = nvmem_cell_read(cell, &len);
667 +
668 + nvmem_cell_put(cell);
669 +
670 + if (IS_ERR(efuse)) {
671 + dev_err(dev, "Failed to read cell '%s'\n", cell_name);
672 + return PTR_ERR(efuse);
673 + }
674 +
675 + lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
676 + lvts_td->calib_len + len, GFP_KERNEL);
677 + if (!lvts_td->calib)
678 + return -ENOMEM;
679 +
680 + memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
681 +
682 + lvts_td->calib_len += len;
683 +
684 + kfree(efuse);
685 + }
686 +
687 + return 0;
688 +}
689 +
690 +static int lvts_golden_temp_init(struct device *dev, u32 *value)
691 +{
692 + u32 gt;
693 +
694 + gt = (*value) >> 24;
695 +
696 + if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
697 + golden_temp = gt;
698 +
699 + coeff_b = golden_temp * 500 + LVTS_COEFF_B;
700 +
701 + return 0;
702 +}
703 +
704 +static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
705 + const struct lvts_data *lvts_data)
706 +{
707 + size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
708 + struct lvts_ctrl *lvts_ctrl;
709 + int i, ret;
710 +
711 + /*
712 + * Create the calibration bytes stream from efuse data
713 + */
714 + ret = lvts_calibration_read(dev, lvts_td, lvts_data);
715 + if (ret)
716 + return ret;
717 +
718 + /*
719 + * The golden temp information is contained in the first chunk
720 + * of efuse data.
721 + */
722 + ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
723 + if (ret)
724 + return ret;
725 +
726 + lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
727 + if (!lvts_ctrl)
728 + return -ENOMEM;
729 +
730 + for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
731 +
732 + lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
733 +
734 + ret = lvts_sensor_init(dev, &lvts_ctrl[i],
735 + &lvts_data->lvts_ctrl[i]);
736 + if (ret)
737 + return ret;
738 +
739 + ret = lvts_calibration_init(dev, &lvts_ctrl[i],
740 + &lvts_data->lvts_ctrl[i],
741 + lvts_td->calib);
742 + if (ret)
743 + return ret;
744 +
745 + /*
746 + * The mode the ctrl will use to read the temperature
747 + * (filtered or immediate)
748 + */
749 + lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
750 +
751 + /*
752 + * The temperature to raw temperature must be done
753 + * after initializing the calibration.
754 + */
755 + lvts_ctrl[i].hw_tshut_raw_temp =
756 + lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
757 + }
758 +
759 + /*
760 + * We no longer need the efuse bytes stream, let's free it
761 + */
762 + devm_kfree(dev, lvts_td->calib);
763 +
764 + lvts_td->lvts_ctrl = lvts_ctrl;
765 + lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
766 +
767 + return 0;
768 +}
769 +
770 +/*
771 + * At this point the configuration register is the only place in the
772 + * driver where we write multiple values. Per hardware constraint,
773 + * each write in the configuration register must be separated by a
774 + * delay of 2 us.
775 + */
776 +static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
777 +{
778 + int i;
779 +
780 + /*
781 + * Configuration register
782 + */
783 + for (i = 0; i < nr_cmds; i++) {
784 + writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
785 + usleep_range(2, 4);
786 + }
787 +}
788 +
789 +static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
790 +{
791 + /*
792 + * LVTS_PROTCTL : Thermal Protection Sensor Selection
793 + *
794 + * Bits:
795 + *
796 + * 19-18 : Sensor to base the protection on
797 + * 17-16 : Strategy:
798 + * 00 : Average of 4 sensors
799 + * 01 : Max of 4 sensors
800 + * 10 : Selected sensor with bits 19-18
801 + * 11 : Reserved
802 + */
803 + writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base));
804 +
805 + /*
806 + * LVTS_PROTTA : Stage 1 temperature threshold
807 + * LVTS_PROTTB : Stage 2 temperature threshold
808 + * LVTS_PROTTC : Stage 3 temperature threshold
809 + *
810 + * Bits:
811 + *
812 + * 14-0: Raw temperature threshold
813 + *
814 + * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
815 + * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
816 + */
817 + writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base));
818 +
819 + /*
820 + * LVTS_MONINT : Interrupt configuration register
821 + *
822 + * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
823 + * register, except we set the bits to enable the interrupt.
824 + */
825 + writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
826 +
827 + return 0;
828 +}
829 +
830 +static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
831 +{
832 + int ret;
833 +
834 + ret = reset_control_assert(reset);
835 + if (ret)
836 + return ret;
837 +
838 + return reset_control_deassert(reset);
839 +}
840 +
841 +/*
842 + * Enable or disable the clocks of a specified thermal controller
843 + */
844 +static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
845 +{
846 + /*
847 + * LVTS_CLKEN : Internal LVTS clock
848 + *
849 + * Bits:
850 + *
851 + * 0 : enable / disable clock
852 + */
853 + writel(enable, LVTS_CLKEN(lvts_ctrl->base));
854 +
855 + return 0;
856 +}
857 +
858 +static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
859 +{
860 + u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
861 +
862 + lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
863 +
864 + /*
865 + * LVTS_ID : Get ID and status of the thermal controller
866 + *
867 + * Bits:
868 + *
869 + * 0-5 : thermal controller id
870 + * 7 : thermal controller connection is valid
871 + */
872 + id = readl(LVTS_ID(lvts_ctrl->base));
873 + if (!(id & BIT(7)))
874 + return -EIO;
875 +
876 + return 0;
877 +}
878 +
879 +static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
880 +{
881 + /*
882 + * Write device mask: 0xC1030000
883 + */
884 + u32 cmds[] = {
885 + 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
886 + 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
887 + 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
888 + 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
889 + };
890 +
891 + lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
892 +
893 + return 0;
894 +}
895 +
896 +static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
897 +{
898 + int i;
899 + void __iomem *lvts_edata[] = {
900 + LVTS_EDATA00(lvts_ctrl->base),
901 + LVTS_EDATA01(lvts_ctrl->base),
902 + LVTS_EDATA02(lvts_ctrl->base),
903 + LVTS_EDATA03(lvts_ctrl->base)
904 + };
905 +
906 + /*
907 + * LVTS_EDATA0X : Efuse calibration reference value for sensor X
908 + *
909 + * Bits:
910 + *
911 + * 20-0 : Efuse value for normalization data
912 + */
913 + for (i = 0; i < LVTS_SENSOR_MAX; i++)
914 + writel(lvts_ctrl->calibration[i], lvts_edata[i]);
915 +
916 + return 0;
917 +}
918 +
919 +static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
920 +{
921 + u32 value;
922 +
923 + /*
924 + * LVTS_TSSEL : Sensing point index numbering
925 + *
926 + * Bits:
927 + *
928 + * 31-24: ADC Sense 3
929 + * 23-16: ADC Sense 2
930 + * 15-8 : ADC Sense 1
931 + * 7-0 : ADC Sense 0
932 + */
933 + value = LVTS_TSSEL_CONF;
934 + writel(value, LVTS_TSSEL(lvts_ctrl->base));
935 +
936 + /*
937 + * LVTS_CALSCALE : ADC voltage round
938 + */
939 + value = 0x300;
940 + value = LVTS_CALSCALE_CONF;
941 +
942 + /*
943 + * LVTS_MSRCTL0 : Sensor filtering strategy
944 + *
945 + * Filters:
946 + *
947 + * 000 : One sample
948 + * 001 : Avg 2 samples
949 + * 010 : 4 samples, drop min and max, avg 2 samples
950 + * 011 : 6 samples, drop min and max, avg 4 samples
951 + * 100 : 10 samples, drop min and max, avg 8 samples
952 + * 101 : 18 samples, drop min and max, avg 16 samples
953 + *
954 + * Bits:
955 + *
956 + * 0-2 : Sensor0 filter
957 + * 3-5 : Sensor1 filter
958 + * 6-8 : Sensor2 filter
959 + * 9-11 : Sensor3 filter
960 + */
961 + value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 |
962 + LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
963 + writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
964 +
965 + /*
966 + * LVTS_MSRCTL1 : Measurement control
967 + *
968 + * Bits:
969 + *
970 + * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
971 + * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
972 + * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
973 + * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
974 + *
975 + * That configuration will ignore the filtering and the delays
976 + * introduced below in MONCTL1 and MONCTL2
977 + */
978 + if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
979 + value = BIT(9) | BIT(6) | BIT(5) | BIT(4);
980 + writel(value, LVTS_MSRCTL1(lvts_ctrl->base));
981 + }
982 +
983 + /*
984 + * LVTS_MONCTL1 : Period unit and group interval configuration
985 + *
986 + * The clock source of LVTS thermal controller is 26MHz.
987 + *
988 + * The period unit is a time base for all the interval delays
989 + * specified in the registers. By default we use 12. The time
990 + * conversion is done by multiplying by 256 and 1/26.10^6
991 + *
992 + * An interval delay multiplied by the period unit gives the
993 + * duration in seconds.
994 + *
995 + * - Filter interval delay is a delay between two samples of
996 + * the same sensor.
997 + *
998 + * - Sensor interval delay is a delay between two samples of
999 + * different sensors.
1000 + *
1001 + * - Group interval delay is a delay between different rounds.
1002 + *
1003 + * For example:
1004 + * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
1005 + * and two sensors, TS1 and TS2, are in a LVTS thermal controller
1006 + * and then
1007 + * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
1008 + * Filter interval delay = 1 * Period unit = 118.149us
1009 + * Sensor interval delay = 2 * Period unit = 236.298us
1010 + * Group interval delay = 1 * Period unit = 118.149us
1011 + *
1012 + * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1...
1013 + * <--> Filter interval delay
1014 + * <--> Sensor interval delay
1015 + * <--> Group interval delay
1016 + * Bits:
1017 + * 29 - 20 : Group interval
1018 + * 16 - 13 : Send a single interrupt when crossing the hot threshold (1)
1019 + * or an interrupt everytime the hot threshold is crossed (0)
1020 + * 9 - 0 : Period unit
1021 + *
1022 + */
1023 + value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
1024 + writel(value, LVTS_MONCTL1(lvts_ctrl->base));
1025 +
1026 + /*
1027 + * LVTS_MONCTL2 : Filtering and sensor interval
1028 + *
1029 + * Bits:
1030 + *
1031 + * 25-16 : Interval unit in PERIOD_UNIT between sample on
1032 + * the same sensor, filter interval
1033 + * 9-0 : Interval unit in PERIOD_UNIT between each sensor
1034 + *
1035 + */
1036 + value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
1037 + writel(value, LVTS_MONCTL2(lvts_ctrl->base));
1038 +
1039 + return lvts_irq_init(lvts_ctrl);
1040 +}
1041 +
1042 +static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1043 +{
1044 + struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
1045 + struct thermal_zone_device *tz;
1046 + u32 sensor_map = 0;
1047 + int i;
1048 +
1049 + for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
1050 +
1051 + int dt_id = lvts_sensors[i].dt_id;
1052 +
1053 + tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
1054 + &lvts_ops);
1055 + if (IS_ERR(tz)) {
1056 + /*
1057 + * This thermal zone is not described in the
1058 + * device tree. It is not an error from the
1059 + * thermal OF code POV, we just continue.
1060 + */
1061 + if (PTR_ERR(tz) == -ENODEV)
1062 + continue;
1063 +
1064 + return PTR_ERR(tz);
1065 + }
1066 +
1067 + /*
1068 + * The thermal zone pointer will be needed in the
1069 + * interrupt handler, we store it in the sensor
1070 + * structure. The thermal domain structure will be
1071 + * passed to the interrupt handler private data as the
1072 + * interrupt is shared for all the controller
1073 + * belonging to the thermal domain.
1074 + */
1075 + lvts_sensors[i].tz = tz;
1076 +
1077 + /*
1078 + * This sensor was correctly associated with a thermal
1079 + * zone, let's set the corresponding bit in the sensor
1080 + * map, so we can enable the temperature monitoring in
1081 + * the hardware thermal controller.
1082 + */
1083 + sensor_map |= BIT(i);
1084 + }
1085 +
1086 + /*
1087 + * Bits:
1088 + * 9: Single point access flow
1089 + * 0-3: Enable sensing point 0-3
1090 + *
1091 + * The initialization of the thermal zones give us
1092 + * which sensor point to enable. If any thermal zone
1093 + * was not described in the device tree, it won't be
1094 + * enabled here in the sensor map.
1095 + */
1096 + writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
1097 +
1098 + return 0;
1099 +}
1100 +
1101 +static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
1102 + const struct lvts_data *lvts_data)
1103 +{
1104 + struct lvts_ctrl *lvts_ctrl;
1105 + int i, ret;
1106 +
1107 + ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
1108 + if (ret)
1109 + return ret;
1110 +
1111 + ret = lvts_domain_reset(dev, lvts_td->reset);
1112 + if (ret) {
1113 + dev_dbg(dev, "Failed to reset domain");
1114 + return ret;
1115 + }
1116 +
1117 + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1118 +
1119 + lvts_ctrl = &lvts_td->lvts_ctrl[i];
1120 +
1121 + /*
1122 + * Initialization steps:
1123 + *
1124 + * - Enable the clock
1125 + * - Connect to the LVTS
1126 + * - Initialize the LVTS
1127 + * - Prepare the calibration data
1128 + * - Select monitored sensors
1129 + * [ Configure sampling ]
1130 + * [ Configure the interrupt ]
1131 + * - Start measurement
1132 + */
1133 + ret = lvts_ctrl_set_enable(lvts_ctrl, true);
1134 + if (ret) {
1135 + dev_dbg(dev, "Failed to enable LVTS clock");
1136 + return ret;
1137 + }
1138 +
1139 + ret = lvts_ctrl_connect(dev, lvts_ctrl);
1140 + if (ret) {
1141 + dev_dbg(dev, "Failed to connect to LVTS controller");
1142 + return ret;
1143 + }
1144 +
1145 + ret = lvts_ctrl_initialize(dev, lvts_ctrl);
1146 + if (ret) {
1147 + dev_dbg(dev, "Failed to initialize controller");
1148 + return ret;
1149 + }
1150 +
1151 + ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
1152 + if (ret) {
1153 + dev_dbg(dev, "Failed to calibrate controller");
1154 + return ret;
1155 + }
1156 +
1157 + ret = lvts_ctrl_configure(dev, lvts_ctrl);
1158 + if (ret) {
1159 + dev_dbg(dev, "Failed to configure controller");
1160 + return ret;
1161 + }
1162 +
1163 + ret = lvts_ctrl_start(dev, lvts_ctrl);
1164 + if (ret) {
1165 + dev_dbg(dev, "Failed to start controller");
1166 + return ret;
1167 + }
1168 + }
1169 +
1170 + return lvts_debugfs_init(dev, lvts_td);
1171 +}
1172 +
1173 +static int lvts_probe(struct platform_device *pdev)
1174 +{
1175 + const struct lvts_data *lvts_data;
1176 + struct lvts_domain *lvts_td;
1177 + struct device *dev = &pdev->dev;
1178 + struct resource *res;
1179 + int irq, ret;
1180 +
1181 + lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
1182 + if (!lvts_td)
1183 + return -ENOMEM;
1184 +
1185 + lvts_data = of_device_get_match_data(dev);
1186 +
1187 + lvts_td->clk = devm_clk_get_enabled(dev, NULL);
1188 + if (IS_ERR(lvts_td->clk))
1189 + return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
1190 +
1191 + res = platform_get_mem_or_io(pdev, 0);
1192 + if (!res)
1193 + return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
1194 +
1195 + lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1196 + if (IS_ERR(lvts_td->base))
1197 + return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
1198 +
1199 + lvts_td->reset = devm_reset_control_get_by_index(dev, 0);
1200 + if (IS_ERR(lvts_td->reset))
1201 + return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
1202 +
1203 + irq = platform_get_irq(pdev, 0);
1204 + if (irq < 0)
1205 + return dev_err_probe(dev, irq, "No irq resource\n");
1206 +
1207 + ret = lvts_domain_init(dev, lvts_td, lvts_data);
1208 + if (ret)
1209 + return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
1210 +
1211 + /*
1212 + * At this point the LVTS is initialized and enabled. We can
1213 + * safely enable the interrupt.
1214 + */
1215 + ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
1216 + IRQF_ONESHOT, dev_name(dev), lvts_td);
1217 + if (ret)
1218 + return dev_err_probe(dev, ret, "Failed to request interrupt\n");
1219 +
1220 + platform_set_drvdata(pdev, lvts_td);
1221 +
1222 + return 0;
1223 +}
1224 +
1225 +static int lvts_remove(struct platform_device *pdev)
1226 +{
1227 + struct lvts_domain *lvts_td;
1228 + int i;
1229 +
1230 + lvts_td = platform_get_drvdata(pdev);
1231 +
1232 + for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
1233 + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1234 +
1235 + lvts_debugfs_exit(lvts_td);
1236 +
1237 + return 0;
1238 +}
1239 +
1240 +static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
1241 + {
1242 + .cal_offset = { 0x04, 0x07 },
1243 + .lvts_sensor = {
1244 + { .dt_id = MT8195_MCU_BIG_CPU0 },
1245 + { .dt_id = MT8195_MCU_BIG_CPU1 }
1246 + },
1247 + .num_lvts_sensor = 2,
1248 + .offset = 0x0,
1249 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1250 + },
1251 + {
1252 + .cal_offset = { 0x0d, 0x10 },
1253 + .lvts_sensor = {
1254 + { .dt_id = MT8195_MCU_BIG_CPU2 },
1255 + { .dt_id = MT8195_MCU_BIG_CPU3 }
1256 + },
1257 + .num_lvts_sensor = 2,
1258 + .offset = 0x100,
1259 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1260 + },
1261 + {
1262 + .cal_offset = { 0x16, 0x19, 0x1c, 0x1f },
1263 + .lvts_sensor = {
1264 + { .dt_id = MT8195_MCU_LITTLE_CPU0 },
1265 + { .dt_id = MT8195_MCU_LITTLE_CPU1 },
1266 + { .dt_id = MT8195_MCU_LITTLE_CPU2 },
1267 + { .dt_id = MT8195_MCU_LITTLE_CPU3 }
1268 + },
1269 + .num_lvts_sensor = 4,
1270 + .offset = 0x200,
1271 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1272 + }
1273 +};
1274 +
1275 +static const struct lvts_data mt8195_lvts_mcu_data = {
1276 + .lvts_ctrl = mt8195_lvts_data_ctrl,
1277 + .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl),
1278 +};
1279 +
1280 +static const struct of_device_id lvts_of_match[] = {
1281 + { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
1282 + {},
1283 +};
1284 +MODULE_DEVICE_TABLE(of, lvts_of_match);
1285 +
1286 +static struct platform_driver lvts_driver = {
1287 + .probe = lvts_probe,
1288 + .remove = lvts_remove,
1289 + .driver = {
1290 + .name = "mtk-lvts-thermal",
1291 + .of_match_table = lvts_of_match,
1292 + },
1293 +};
1294 +module_platform_driver(lvts_driver);
1295 +
1296 +MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>");
1297 +MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
1298 +MODULE_LICENSE("GPL");
Staging tree of Sander Vanheule