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1 From 8747ec2e9762ed9ae53b3a590938f454b6a1abdf Mon Sep 17 00:00:00 2001
2 From: Vincent Shih <vincent.sunplus@gmail.com>
3 Date: Wed, 23 Feb 2022 22:35:01 +0000
4 Subject: [PATCH] nvmem: Add driver for OCOTP in Sunplus SP7021
5
6 Add driver for OCOTP in Sunplus SP7021
7
8 Signed-off-by: Vincent Shih <vincent.sunplus@gmail.com>
9 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
10 Link: https://lore.kernel.org/r/20220223223502.29454-3-srinivas.kandagatla@linaro.org
11 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
12 ---
13 MAINTAINERS | 5 +
14 drivers/nvmem/Kconfig | 12 ++
15 drivers/nvmem/Makefile | 2 +
16 drivers/nvmem/sunplus-ocotp.c | 228 ++++++++++++++++++++++++++++++++++
17 4 files changed, 247 insertions(+)
18 create mode 100644 drivers/nvmem/sunplus-ocotp.c
19
20 --- a/MAINTAINERS
21 +++ b/MAINTAINERS
22 @@ -17962,6 +17962,11 @@ L: netdev@vger.kernel.org
23 S: Maintained
24 F: drivers/net/ethernet/dlink/sundance.c
25
26 +SUNPLUS OCOTP DRIVER
27 +M: Vincent Shih <vincent.sunplus@gmail.com>
28 +S: Maintained
29 +F: drivers/nvmem/sunplus-ocotp.c
30 +
31 SUPERH
32 M: Yoshinori Sato <ysato@users.sourceforge.jp>
33 M: Rich Felker <dalias@libc.org>
34 --- a/drivers/nvmem/Kconfig
35 +++ b/drivers/nvmem/Kconfig
36 @@ -312,4 +312,16 @@ config NVMEM_LAYERSCAPE_SFP
37 This driver can also be built as a module. If so, the module
38 will be called layerscape-sfp.
39
40 +config NVMEM_SUNPLUS_OCOTP
41 + tristate "Sunplus SoC OTP support"
42 + depends on SOC_SP7021 || COMPILE_TEST
43 + depends on HAS_IOMEM
44 + help
45 + This is a driver for the On-chip OTP controller (OCOTP) available
46 + on Sunplus SoCs. It provides access to 128 bytes of one-time
47 + programmable eFuse.
48 +
49 + This driver can also be built as a module. If so, the module
50 + will be called nvmem-sunplus-ocotp.
51 +
52 endif
53 --- a/drivers/nvmem/Makefile
54 +++ b/drivers/nvmem/Makefile
55 @@ -63,3 +63,5 @@ obj-$(CONFIG_NVMEM_BRCM_NVRAM) += nvmem_
56 nvmem_brcm_nvram-y := brcm_nvram.o
57 obj-$(CONFIG_NVMEM_LAYERSCAPE_SFP) += nvmem-layerscape-sfp.o
58 nvmem-layerscape-sfp-y := layerscape-sfp.o
59 +obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o
60 +nvmem_sunplus_ocotp-y := sunplus-ocotp.o
61 --- /dev/null
62 +++ b/drivers/nvmem/sunplus-ocotp.c
63 @@ -0,0 +1,228 @@
64 +// SPDX-License-Identifier: GPL-2.0
65 +
66 +/*
67 + * The OCOTP driver for Sunplus SP7021
68 + *
69 + * Copyright (C) 2019 Sunplus Technology Inc., All rights reserved.
70 + */
71 +
72 +#include <linux/bitfield.h>
73 +#include <linux/clk.h>
74 +#include <linux/delay.h>
75 +#include <linux/device.h>
76 +#include <linux/io.h>
77 +#include <linux/iopoll.h>
78 +#include <linux/module.h>
79 +#include <linux/nvmem-provider.h>
80 +#include <linux/of_device.h>
81 +#include <linux/platform_device.h>
82 +
83 +/*
84 + * OTP memory
85 + * Each bank contains 4 words (32 bits).
86 + * Bank 0 starts at offset 0 from the base.
87 + */
88 +
89 +#define OTP_WORDS_PER_BANK 4
90 +#define OTP_WORD_SIZE sizeof(u32)
91 +#define OTP_BIT_ADDR_OF_BANK (8 * OTP_WORD_SIZE * OTP_WORDS_PER_BANK)
92 +#define QAC628_OTP_NUM_BANKS 8
93 +#define QAC628_OTP_SIZE (QAC628_OTP_NUM_BANKS * OTP_WORDS_PER_BANK * OTP_WORD_SIZE)
94 +#define OTP_READ_TIMEOUT_US 200000
95 +
96 +/* HB_GPIO */
97 +#define ADDRESS_8_DATA 0x20
98 +
99 +/* OTP_RX */
100 +#define OTP_CONTROL_2 0x48
101 +#define OTP_RD_PERIOD GENMASK(15, 8)
102 +#define OTP_RD_PERIOD_MASK ~GENMASK(15, 8)
103 +#define CPU_CLOCK FIELD_PREP(OTP_RD_PERIOD, 30)
104 +#define SEL_BAK_KEY2 BIT(5)
105 +#define SEL_BAK_KEY2_MASK ~BIT(5)
106 +#define SW_TRIM_EN BIT(4)
107 +#define SW_TRIM_EN_MASK ~BIT(4)
108 +#define SEL_BAK_KEY BIT(3)
109 +#define SEL_BAK_KEY_MASK ~BIT(3)
110 +#define OTP_READ BIT(2)
111 +#define OTP_LOAD_SECURE_DATA BIT(1)
112 +#define OTP_LOAD_SECURE_DATA_MASK ~BIT(1)
113 +#define OTP_DO_CRC BIT(0)
114 +#define OTP_DO_CRC_MASK ~BIT(0)
115 +#define OTP_STATUS 0x4c
116 +#define OTP_READ_DONE BIT(4)
117 +#define OTP_READ_DONE_MASK ~BIT(4)
118 +#define OTP_LOAD_SECURE_DONE_MASK ~BIT(2)
119 +#define OTP_READ_ADDRESS 0x50
120 +
121 +enum base_type {
122 + HB_GPIO,
123 + OTPRX,
124 + BASEMAX,
125 +};
126 +
127 +struct sp_ocotp_priv {
128 + struct device *dev;
129 + void __iomem *base[BASEMAX];
130 + struct clk *clk;
131 +};
132 +
133 +struct sp_ocotp_data {
134 + int size;
135 +};
136 +
137 +const struct sp_ocotp_data sp_otp_v0 = {
138 + .size = QAC628_OTP_SIZE,
139 +};
140 +
141 +static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value)
142 +{
143 + unsigned int addr_data;
144 + unsigned int byte_shift;
145 + unsigned int status;
146 + int ret;
147 +
148 + addr_data = addr % (OTP_WORD_SIZE * OTP_WORDS_PER_BANK);
149 + addr_data = addr_data / OTP_WORD_SIZE;
150 +
151 + byte_shift = addr % (OTP_WORD_SIZE * OTP_WORDS_PER_BANK);
152 + byte_shift = byte_shift % OTP_WORD_SIZE;
153 +
154 + addr = addr / (OTP_WORD_SIZE * OTP_WORDS_PER_BANK);
155 + addr = addr * OTP_BIT_ADDR_OF_BANK;
156 +
157 + writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK &
158 + OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS);
159 + writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS);
160 + writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ,
161 + otp->base[OTPRX] + OTP_CONTROL_2);
162 + writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) & SEL_BAK_KEY2_MASK & SW_TRIM_EN_MASK
163 + & SEL_BAK_KEY_MASK & OTP_LOAD_SECURE_DATA_MASK & OTP_DO_CRC_MASK,
164 + otp->base[OTPRX] + OTP_CONTROL_2);
165 + writel((readl(otp->base[OTPRX] + OTP_CONTROL_2) & OTP_RD_PERIOD_MASK) | CPU_CLOCK,
166 + otp->base[OTPRX] + OTP_CONTROL_2);
167 +
168 + ret = readl_poll_timeout(otp->base[OTPRX] + OTP_STATUS, status,
169 + status & OTP_READ_DONE, 10, OTP_READ_TIMEOUT_US);
170 +
171 + if (ret < 0)
172 + return ret;
173 +
174 + *value = (readl(otp->base[HB_GPIO] + ADDRESS_8_DATA + addr_data * OTP_WORD_SIZE)
175 + >> (8 * byte_shift)) & 0xff;
176 +
177 + return ret;
178 +}
179 +
180 +static int sp_ocotp_read(void *priv, unsigned int offset, void *value, size_t bytes)
181 +{
182 + struct sp_ocotp_priv *otp = priv;
183 + unsigned int addr;
184 + char *buf = value;
185 + char val[4];
186 + int ret;
187 +
188 + ret = clk_enable(otp->clk);
189 + if (ret)
190 + return ret;
191 +
192 + *buf = 0;
193 + for (addr = offset; addr < (offset + bytes); addr++) {
194 + ret = sp_otp_read_real(otp, addr, val);
195 + if (ret < 0) {
196 + dev_err(otp->dev, "OTP read fail:%d at %d", ret, addr);
197 + goto disable_clk;
198 + }
199 +
200 + *buf++ = *val;
201 + }
202 +
203 +disable_clk:
204 + clk_disable(otp->clk);
205 +
206 + return ret;
207 +}
208 +
209 +static struct nvmem_config sp_ocotp_nvmem_config = {
210 + .name = "sp-ocotp",
211 + .read_only = true,
212 + .word_size = 1,
213 + .size = QAC628_OTP_SIZE,
214 + .stride = 1,
215 + .reg_read = sp_ocotp_read,
216 + .owner = THIS_MODULE,
217 +};
218 +
219 +static int sp_ocotp_probe(struct platform_device *pdev)
220 +{
221 + struct device *dev = &pdev->dev;
222 + struct nvmem_device *nvmem;
223 + struct sp_ocotp_priv *otp;
224 + struct resource *res;
225 + int ret;
226 +
227 + otp = devm_kzalloc(dev, sizeof(*otp), GFP_KERNEL);
228 + if (!otp)
229 + return -ENOMEM;
230 +
231 + otp->dev = dev;
232 +
233 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hb_gpio");
234 + otp->base[HB_GPIO] = devm_ioremap_resource(dev, res);
235 + if (IS_ERR(otp->base[HB_GPIO]))
236 + return PTR_ERR(otp->base[HB_GPIO]);
237 +
238 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otprx");
239 + otp->base[OTPRX] = devm_ioremap_resource(dev, res);
240 + if (IS_ERR(otp->base[OTPRX]))
241 + return PTR_ERR(otp->base[OTPRX]);
242 +
243 + otp->clk = devm_clk_get(&pdev->dev, NULL);
244 + if (IS_ERR(otp->clk))
245 + return dev_err_probe(&pdev->dev, PTR_ERR(otp->clk),
246 + "devm_clk_get fail\n");
247 +
248 + ret = clk_prepare(otp->clk);
249 + if (ret < 0) {
250 + dev_err(dev, "failed to prepare clk: %d\n", ret);
251 + return ret;
252 + }
253 +
254 + sp_ocotp_nvmem_config.priv = otp;
255 + sp_ocotp_nvmem_config.dev = dev;
256 +
257 + nvmem = devm_nvmem_register(dev, &sp_ocotp_nvmem_config);
258 + if (IS_ERR(nvmem))
259 + return dev_err_probe(&pdev->dev, PTR_ERR(nvmem),
260 + "register nvmem device fail\n");
261 +
262 + platform_set_drvdata(pdev, nvmem);
263 +
264 + dev_dbg(dev, "banks:%d x wpb:%d x wsize:%d = %d",
265 + (int)QAC628_OTP_NUM_BANKS, (int)OTP_WORDS_PER_BANK,
266 + (int)OTP_WORD_SIZE, (int)QAC628_OTP_SIZE);
267 +
268 + dev_info(dev, "by Sunplus (C) 2020");
269 +
270 + return 0;
271 +}
272 +
273 +static const struct of_device_id sp_ocotp_dt_ids[] = {
274 + { .compatible = "sunplus,sp7021-ocotp", .data = &sp_otp_v0 },
275 + { }
276 +};
277 +MODULE_DEVICE_TABLE(of, sp_ocotp_dt_ids);
278 +
279 +static struct platform_driver sp_otp_driver = {
280 + .probe = sp_ocotp_probe,
281 + .driver = {
282 + .name = "sunplus,sp7021-ocotp",
283 + .of_match_table = sp_ocotp_dt_ids,
284 + }
285 +};
286 +module_platform_driver(sp_otp_driver);
287 +
288 +MODULE_AUTHOR("Vincent Shih <vincent.sunplus@gmail.com>");
289 +MODULE_DESCRIPTION("Sunplus On-Chip OTP driver");
290 +MODULE_LICENSE("GPL");
291 +
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