1 From 3fed02d930597c53f1c8500aff14581bb87a1e3d Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 20 May 2022 11:22:31 +0800
4 Subject: [PATCH 07/25] doc: mediatek: add documentation for mt7621 reference
7 The MT7621 requires external binary blob being executed during u-boot's
8 boot-up flow. It's necessary to provide a guide here for users to correctly
11 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
12 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
14 doc/board/index.rst | 1 +
15 doc/board/mediatek/index.rst | 9 +++++++
16 doc/board/mediatek/mt7621.rst | 48 +++++++++++++++++++++++++++++++++++
17 3 files changed, 58 insertions(+)
18 create mode 100644 doc/board/mediatek/index.rst
19 create mode 100644 doc/board/mediatek/mt7621.rst
21 diff --git a/doc/board/index.rst b/doc/board/index.rst
22 index f90a9cad45..01b99f9cf5 100644
23 --- a/doc/board/index.rst
24 +++ b/doc/board/index.rst
25 @@ -23,6 +23,7 @@ Board-specific doc
33 diff --git a/doc/board/mediatek/index.rst b/doc/board/mediatek/index.rst
35 index 0000000000..38cd8cb5b2
37 +++ b/doc/board/mediatek/index.rst
39 +.. SPDX-License-Identifier: GPL-2.0+
48 diff --git a/doc/board/mediatek/mt7621.rst b/doc/board/mediatek/mt7621.rst
50 index 0000000000..1662255546
52 +++ b/doc/board/mediatek/mt7621.rst
54 +.. SPDX-License-Identifier: GPL-2.0
56 +mt7621_rfb/mt7621_nand_rfb
57 +==========================
59 +U-Boot for the MediaTek MT7621 boards
64 +- Get the DDR initialization binary blob
65 +- Configure CPU and DDR parameters
68 +Get the DDR initialization binary blob
69 +--------------------------------------
72 + - https://raw.githubusercontent.com/mtk-openwrt/mt7621-lowlevel-preloader/master/mt7621_stage_sram.bin
73 + - https://raw.githubusercontent.com/mtk-openwrt/mt7621-lowlevel-preloader/master/mt7621_stage_sram_noprint.bin
75 +mt7621_stage_sram_noprint.bin has removed all output logs. To use this one,
76 +download and rename it to mt7621_stage_sram.bin
78 +Put the binary blob to the u-boot build directory.
80 +Configure CPU and DDR parameters
81 +--------------------------------
83 +menuconfig > MIPS architecture > MediaTek MIPS platforms > CPU & DDR configuration
85 +Select the correct DDR timing parameters for your board. The size shown here
86 +must match the DDR size of you board.
88 +The frequency of CPU and DDR can also be adjusted.
95 + $ export CROSS_COMPILE=mipsel-linux-
96 + $ make O=build mt7621_rfb_defconfig # or mt7621_nand_rfb_defconfig
97 + $ cp mt7621_stage_sram.bin ./build/mt7621_stage_sram.bin
98 + $ # or cp mt7621_stage_sram_noprint.bin ./build/mt7621_stage_sram.bin
101 +Burn the u-boot-mt7621.bin to the SPI-NOR or NAND flash.