28702c9d0e8bfcb5cdba5e1c49b42fc050d7adc5
[openwrt/openwrt.git] /
1 From def26913b66fd94e431afecf28e09c08e8c02a35 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
3 Date: Fri, 27 Nov 2020 12:14:42 +0100
4 Subject: [PATCH] reset: simple: add BCM4908 MISC PCIe reset controller support
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 It's a trivial reset controller. One register with bit per PCIe core.
10
11 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
12 Acked-by: Florian Fainelli <f.fainelli@gmail.com>
13 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
14 ---
15 drivers/reset/Kconfig | 2 +-
16 drivers/reset/reset-simple.c | 2 ++
17 2 files changed, 3 insertions(+), 1 deletion(-)
18
19 --- a/drivers/reset/Kconfig
20 +++ b/drivers/reset/Kconfig
21 @@ -167,7 +167,7 @@ config RESET_SCMI
22
23 config RESET_SIMPLE
24 bool "Simple Reset Controller Driver" if COMPILE_TEST
25 - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
26 + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
27 help
28 This enables a simple reset controller driver for reset lines that
29 that can be asserted and deasserted by toggling bits in a contiguous,
30 --- a/drivers/reset/reset-simple.c
31 +++ b/drivers/reset/reset-simple.c
32 @@ -146,6 +146,8 @@ static const struct of_device_id reset_s
33 { .compatible = "aspeed,ast2500-lpc-reset" },
34 { .compatible = "bitmain,bm1880-reset",
35 .data = &reset_simple_active_low },
36 + { .compatible = "brcm,bcm4908-misc-pcie-reset",
37 + .data = &reset_simple_active_low },
38 { .compatible = "snps,dw-high-reset" },
39 { .compatible = "snps,dw-low-reset",
40 .data = &reset_simple_active_low },