git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 3831266fedf14ef415791a93dd03a9e637eb8b5e Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Tue, 26 Jul 2022 09:24:13 +0800
   4 Subject: [PATCH 05/31] mmc: mediatek: add support for MediaTek MT7891/MT7986
   5  SoCs
   6
   7 Add eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs
   8 Both chips support SDXC and eMMC 4.5. MT7986A supports eMMC 5.1.
   9
  10 Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
  11 Reviewed-by: Simon Glass <sjg@chromium.org>
  12 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  13 ---
  14  drivers/mmc/mtk-sd.c | 68 ++++++++++++++++++++++++++++++++++----------
  15  1 file changed, 53 insertions(+), 15 deletions(-)
  16
  17 --- a/drivers/mmc/mtk-sd.c
  18 +++ b/drivers/mmc/mtk-sd.c
  19 @@ -1496,7 +1496,12 @@ static void msdc_init_hw(struct msdc_hos
  20         /* Enable data & cmd interrupts */
  21         writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
  22
  23 -       writel(0, tune_reg);
  24 +       if (host->top_base) {
  25 +               writel(0, &host->top_base->emmc_top_control);
  26 +               writel(0, &host->top_base->emmc_top_cmd);
  27 +       } else {
  28 +               writel(0, tune_reg);
  29 +       }
  30         writel(0, &host->base->msdc_iocon);
  31
  32         if (host->r_smpl)
  33 @@ -1507,9 +1512,14 @@ static void msdc_init_hw(struct msdc_hos
  34         writel(0x403c0046, &host->base->patch_bit0);
  35         writel(0xffff4089, &host->base->patch_bit1);
  36
  37 -       if (host->dev_comp->stop_clk_fix)
  38 +       if (host->dev_comp->stop_clk_fix) {
  39                 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
  40                                 3 << MSDC_PB1_STOP_DLY_S);
  41 +               clrbits_le32(&host->base->sdc_fifo_cfg,
  42 +                            SDC_FIFO_CFG_WRVALIDSEL);
  43 +               clrbits_le32(&host->base->sdc_fifo_cfg,
  44 +                            SDC_FIFO_CFG_RDVALIDSEL);
  45 +       }
  46
  47         if (host->dev_comp->busy_check)
  48                 clrbits_le32(&host->base->patch_bit1, (1 << 7));
  49 @@ -1544,15 +1554,28 @@ static void msdc_init_hw(struct msdc_hos
  50         }
  51
  52         if (host->dev_comp->data_tune) {
  53 -               setbits_le32(tune_reg,
  54 -                            MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
  55 -               clrsetbits_le32(&host->base->patch_bit0,
  56 -                               MSDC_INT_DAT_LATCH_CK_SEL_M,
  57 -                               host->latch_ck <<
  58 -                               MSDC_INT_DAT_LATCH_CK_SEL_S);
  59 +               if (host->top_base) {
  60 +                       setbits_le32(&host->top_base->emmc_top_control,
  61 +                                    PAD_DAT_RD_RXDLY_SEL);
  62 +                       clrbits_le32(&host->top_base->emmc_top_control,
  63 +                                    DATA_K_VALUE_SEL);
  64 +                       setbits_le32(&host->top_base->emmc_top_cmd,
  65 +                                    PAD_CMD_RD_RXDLY_SEL);
  66 +               } else {
  67 +                       setbits_le32(tune_reg,
  68 +                                    MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
  69 +                       clrsetbits_le32(&host->base->patch_bit0,
  70 +                                       MSDC_INT_DAT_LATCH_CK_SEL_M,
  71 +                                       host->latch_ck <<
  72 +                                       MSDC_INT_DAT_LATCH_CK_SEL_S);
  73 +               }
  74         } else {
  75                 /* choose clock tune */
  76 -               setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
  77 +               if (host->top_base)
  78 +                       setbits_le32(&host->top_base->emmc_top_control,
  79 +                                    PAD_RXDLY_SEL);
  80 +               else
  81 +                       setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
  82         }
  83
  84         if (host->dev_comp->builtin_pad_ctrl) {
  85 @@ -1604,12 +1627,6 @@ static void msdc_init_hw(struct msdc_hos
  86         clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
  87                         3 << SDC_CFG_DTOC_S);
  88
  89 -       if (host->dev_comp->stop_clk_fix) {
  90 -               clrbits_le32(&host->base->sdc_fifo_cfg,
  91 -                            SDC_FIFO_CFG_WRVALIDSEL);
  92 -               clrbits_le32(&host->base->sdc_fifo_cfg,
  93 -                            SDC_FIFO_CFG_RDVALIDSEL);
  94 -       }
  95
  96         host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
  97         host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
  98 @@ -1792,6 +1809,25 @@ static const struct msdc_compatible mt76
  99         .enhance_rx = false
 100  };
 101
 102 +static const struct msdc_compatible mt7986_compat = {
 103 +       .clk_div_bits = 12,
 104 +       .pad_tune0 = true,
 105 +       .async_fifo = true,
 106 +       .data_tune = true,
 107 +       .busy_check = true,
 108 +       .stop_clk_fix = true,
 109 +       .enhance_rx = true,
 110 +};
 111 +
 112 +static const struct msdc_compatible mt7981_compat = {
 113 +       .clk_div_bits = 12,
 114 +       .pad_tune0 = true,
 115 +       .async_fifo = true,
 116 +       .data_tune = true,
 117 +       .busy_check = true,
 118 +       .stop_clk_fix = true,
 119 +};
 120 +
 121  static const struct msdc_compatible mt8512_compat = {
 122         .clk_div_bits = 12,
 123         .pad_tune0 = true,
 124 @@ -1824,6 +1860,8 @@ static const struct udevice_id msdc_ids[
 125         { .compatible = "mediatek,mt7621-mmc", .data = (ulong)&mt7621_compat },
 126         { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
 127         { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
 128 +       { .compatible = "mediatek,mt7986-mmc", .data = (ulong)&mt7986_compat },
 129 +       { .compatible = "mediatek,mt7981-mmc", .data = (ulong)&mt7981_compat },
 130         { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
 131         { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
 132         { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },