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1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
2 Subject: [PATCH] net: phy: cherry-pick Broadcom drivers updates from v4.11
3 MIME-Version: 1.0
4 Content-Type: text/plain; charset=UTF-8
5 Content-Transfer-Encoding: 8bit
6
7 This includes following upstream commits:
8 62e13097c46c net: phy: broadcom: rehook BCM54612E specific init
9 0fc9ae107669 net: phy: broadcom: add support for BCM54210E
10 5e7bfa6cb0a9 net: phy: bcm-phy-lib: clean up remaining AUXCTL register defines
11 8293c7bcdef1 net: phy: broadcom: drop duplicated define for RGMII SKEW delay
12 85b4685da52f net: phy: broadcom: use auxctl reading helper in BCM54612E code
13 039a7b8592ab net: phy: bcm7xxx: Implement EGPHY workaround for 7278
14 582d0ac397ca net: phy: bcm7xxx: Add entry for BCM7278
15
16 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
17 ---
18
19 --- a/drivers/net/phy/bcm7xxx.c
20 +++ b/drivers/net/phy/bcm7xxx.c
21 @@ -163,12 +163,43 @@ static int bcm7xxx_28nm_e0_plus_afe_conf
22 return 0;
23 }
24
25 +static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
26 +{
27 + /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
28 + bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
29 +
30 + /* Cut master bias current by 2% to compensate for RC_CAL offset */
31 + bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
32 +
33 + /* Improve hybrid leakage */
34 + bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
35 +
36 + /* Change rx_on_tune 8 to 0xf */
37 + bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
38 +
39 + /* Change 100Tx EEE bandwidth */
40 + bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
41 +
42 + /* Enable ffe zero detection for Vitesse interoperability */
43 + bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
44 +
45 + r_rc_cal_reset(phydev);
46 +
47 + return 0;
48 +}
49 +
50 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
51 {
52 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
53 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
54 int ret = 0;
55
56 + /* Newer devices have moved the revision information back into a
57 + * standard location in MII_PHYS_ID[23]
58 + */
59 + if (rev == 0)
60 + rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
61 +
62 pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
63 dev_name(&phydev->dev), phydev->drv->name, rev, patch);
64
65 @@ -192,6 +223,9 @@ static int bcm7xxx_28nm_config_init(stru
66 case 0x10:
67 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
68 break;
69 + case 0x01:
70 + ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
71 + break;
72 default:
73 break;
74 }
75 @@ -336,6 +370,7 @@ static int bcm7xxx_suspend(struct phy_de
76
77 static struct phy_driver bcm7xxx_driver[] = {
78 BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
79 + BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
80 BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
81 BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
82 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
83 @@ -350,6 +385,7 @@ static struct phy_driver bcm7xxx_driver[
84
85 static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
86 { PHY_ID_BCM7250, 0xfffffff0, },
87 + { PHY_ID_BCM7278, 0xfffffff0, },
88 { PHY_ID_BCM7364, 0xfffffff0, },
89 { PHY_ID_BCM7366, 0xfffffff0, },
90 { PHY_ID_BCM7346, 0xfffffff0, },
91 --- a/drivers/net/phy/broadcom.c
92 +++ b/drivers/net/phy/broadcom.c
93 @@ -30,6 +30,50 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
94 MODULE_AUTHOR("Maciej W. Rozycki");
95 MODULE_LICENSE("GPL");
96
97 +static int bcm54210e_config_init(struct phy_device *phydev)
98 +{
99 + int val;
100 +
101 + val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
102 + val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
103 + val |= MII_BCM54XX_AUXCTL_MISC_WREN;
104 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
105 +
106 + val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
107 + val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
108 + bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
109 +
110 + return 0;
111 +}
112 +
113 +static int bcm54612e_config_init(struct phy_device *phydev)
114 +{
115 + /* Clear TX internal delay unless requested. */
116 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
117 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
118 + /* Disable TXD to GTXCLK clock delay (default set) */
119 + /* Bit 9 is the only field in shadow register 00011 */
120 + bcm_phy_write_shadow(phydev, 0x03, 0);
121 + }
122 +
123 + /* Clear RX internal delay unless requested. */
124 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
125 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
126 + u16 reg;
127 +
128 + reg = bcm54xx_auxctl_read(phydev,
129 + MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
130 + /* Disable RXD to RXC delay (default set) */
131 + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
132 + /* Clear shadow selector field */
133 + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
134 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
135 + MII_BCM54XX_AUXCTL_MISC_WREN | reg);
136 + }
137 +
138 + return 0;
139 +}
140 +
141 static int bcm54810_config(struct phy_device *phydev)
142 {
143 int rc, val;
144 @@ -230,7 +274,15 @@ static int bcm54xx_config_init(struct ph
145 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
146 bcm54xx_adjust_rxrefclk(phydev);
147
148 - if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
149 + if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
150 + err = bcm54210e_config_init(phydev);
151 + if (err)
152 + return err;
153 + } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
154 + err = bcm54612e_config_init(phydev);
155 + if (err)
156 + return err;
157 + } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
158 err = bcm54810_config(phydev);
159 if (err)
160 return err;
161 @@ -375,41 +427,6 @@ static int bcm5481_config_aneg(struct ph
162 return ret;
163 }
164
165 -static int bcm54612e_config_aneg(struct phy_device *phydev)
166 -{
167 - int ret;
168 -
169 - /* First, auto-negotiate. */
170 - ret = genphy_config_aneg(phydev);
171 -
172 - /* Clear TX internal delay unless requested. */
173 - if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
174 - (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
175 - /* Disable TXD to GTXCLK clock delay (default set) */
176 - /* Bit 9 is the only field in shadow register 00011 */
177 - bcm_phy_write_shadow(phydev, 0x03, 0);
178 - }
179 -
180 - /* Clear RX internal delay unless requested. */
181 - if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
182 - (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
183 - u16 reg;
184 -
185 - /* Errata: reads require filling in the write selector field */
186 - bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
187 - MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
188 - reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
189 - /* Disable RXD to RXC delay (default set) */
190 - reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
191 - /* Clear shadow selector field */
192 - reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
193 - bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
194 - MII_BCM54XX_AUXCTL_MISC_WREN | reg);
195 - }
196 -
197 - return ret;
198 -}
199 -
200 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
201 {
202 int val;
203 @@ -548,6 +565,19 @@ static struct phy_driver broadcom_driver
204 .config_intr = bcm_phy_config_intr,
205 .driver = { .owner = THIS_MODULE },
206 }, {
207 + .phy_id = PHY_ID_BCM54210E,
208 + .phy_id_mask = 0xfffffff0,
209 + .name = "Broadcom BCM54210E",
210 + .features = PHY_GBIT_FEATURES |
211 + SUPPORTED_Pause | SUPPORTED_Asym_Pause,
212 + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
213 + .config_init = bcm54xx_config_init,
214 + .config_aneg = genphy_config_aneg,
215 + .read_status = genphy_read_status,
216 + .ack_interrupt = bcm_phy_ack_intr,
217 + .config_intr = bcm_phy_config_intr,
218 + .driver = { .owner = THIS_MODULE },
219 +}, {
220 .phy_id = PHY_ID_BCM5461,
221 .phy_id_mask = 0xfffffff0,
222 .name = "Broadcom BCM5461",
223 @@ -568,7 +598,7 @@ static struct phy_driver broadcom_driver
224 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
225 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
226 .config_init = bcm54xx_config_init,
227 - .config_aneg = bcm54612e_config_aneg,
228 + .config_aneg = genphy_config_aneg,
229 .read_status = genphy_read_status,
230 .ack_interrupt = bcm_phy_ack_intr,
231 .config_intr = bcm_phy_config_intr,
232 @@ -708,6 +738,7 @@ module_phy_driver(broadcom_drivers);
233 static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
234 { PHY_ID_BCM5411, 0xfffffff0 },
235 { PHY_ID_BCM5421, 0xfffffff0 },
236 + { PHY_ID_BCM54210E, 0xfffffff0 },
237 { PHY_ID_BCM5461, 0xfffffff0 },
238 { PHY_ID_BCM54612E, 0xfffffff0 },
239 { PHY_ID_BCM54616S, 0xfffffff0 },
240 --- a/include/linux/brcmphy.h
241 +++ b/include/linux/brcmphy.h
242 @@ -17,6 +17,7 @@
243 #define PHY_ID_BCM5482 0x0143bcb0
244 #define PHY_ID_BCM5411 0x00206070
245 #define PHY_ID_BCM5421 0x002060e0
246 +#define PHY_ID_BCM54210E 0x600d84a0
247 #define PHY_ID_BCM5464 0x002060b0
248 #define PHY_ID_BCM5461 0x002060c0
249 #define PHY_ID_BCM54612E 0x03625e60
250 @@ -24,6 +25,7 @@
251 #define PHY_ID_BCM57780 0x03625d90
252
253 #define PHY_ID_BCM7250 0xae025280
254 +#define PHY_ID_BCM7278 0xae0251a0
255 #define PHY_ID_BCM7364 0xae025260
256 #define PHY_ID_BCM7366 0x600d8490
257 #define PHY_ID_BCM7346 0x600d8650
258 @@ -103,18 +105,17 @@
259 /*
260 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
261 */
262 -#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
263 +#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
264 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
265 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
266
267 -#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
268 -#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
269 -#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
270 -#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
271 -#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
272 -#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
273 -#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
274 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
275 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
276 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
277 +#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
278 +#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
279
280 +#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
281 #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
282
283 /*
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