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1 From 9e76817056937645205f23ee91e762d5cff5e848 Mon Sep 17 00:00:00 2001
2 From: Luo Jie <quic_luoj@quicinc.com>
3 Date: Mon, 29 Jan 2024 17:57:20 +0800
4 Subject: [PATCH 01/50] dt-bindings: net: Document Qualcomm QCA8084 PHY package
5
6 QCA8084 is quad PHY chip, which integrates 4 PHYs, 2 PCS
7 interfaces (PCS0 and PCS1) and clock controller, which can
8 also be integrated to the switch chip named as QCA8386.
9
10 1. MDIO address of 4 PHYs, 2 PCS and 1 XPCS (PCS1 includes
11 PCS and XPCS, PCS0 includes PCS) can be configured.
12 2. The package mode of PHY is optionally configured for the
13 interface mode of two PCSes working correctly.
14 3. The package level clock and reset need to be initialized.
15 4. The clock and reset per PHY device need to be initialized
16 so that the PHY register can be accessed.
17
18 Change-Id: Idb2338d2673152cbd3c57e95968faa59e9d4a80f
19 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
20 ---
21 .../devicetree/bindings/net/qcom,qca8084.yaml | 198 ++++++++++++++++++
22 include/dt-bindings/net/qcom,qca808x.h | 14 ++
23 2 files changed, 212 insertions(+)
24 create mode 100644 Documentation/devicetree/bindings/net/qcom,qca8084.yaml
25 create mode 100644 include/dt-bindings/net/qcom,qca808x.h
26
27 diff --git a/Documentation/devicetree/bindings/net/qcom,qca8084.yaml b/Documentation/devicetree/bindings/net/qcom,qca8084.yaml
28 new file mode 100644
29 index 000000000000..efa1fa4ebfdc
30 --- /dev/null
31 +++ b/Documentation/devicetree/bindings/net/qcom,qca8084.yaml
32 @@ -0,0 +1,198 @@
33 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
34 +%YAML 1.2
35 +---
36 +$id: http://devicetree.org/schemas/net/qcom,qca8084.yaml#
37 +$schema: http://devicetree.org/meta-schemas/core.yaml#
38 +
39 +title: Qualcomm QCA8084 Ethernet Quad PHY
40 +
41 +maintainers:
42 + - Luo Jie <quic_luoj@quicinc.com>
43 +
44 +description:
45 + Qualcomm QCA8084 is a four-port Ethernet transceiver, the
46 + Ethernet port supports link speed 10/100/1000/2500 Mbps.
47 + There are two PCSes (PCS0 and PCS1) integrated in the PHY
48 + package, PCS1 includes XPCS and PCS to support the interface
49 + mode 10G-QXGMII and SGMII, PCS0 includes a PCS to support the
50 + interface mode SGMII only. There is also a clock controller
51 + integrated in the PHY package. This four-port Ethernet
52 + transceiver can also be integrated to the switch chip named
53 + as QCA8386. The PHY package mode needs to be configured as the
54 + correct value to apply the interface mode of two PCSes as
55 + mentioned below.
56 +
57 + QCA8084 expects an input reference clock 50 MHZ as the clock
58 + source of the integrated clock controller, the integrated
59 + clock controller supplies the clocks and resets to the
60 + integrated PHY, PCS and PHY package.
61 +
62 + - |
63 + +--| |--+-------------------+--| |--+
64 + | PCS1 |<------------+---->| PCS0 |
65 + +-------+ | +-------+
66 + | | |
67 + Ref 50M clk +--------+ | |
68 + ------------>| | clk & rst | |
69 + GPIO Reset |QCA8K_CC+------------+ |
70 + ------------>| | | |
71 + +--------+ | |
72 + | V |
73 + +--------+--------+--------+--------+
74 + | PHY0 | PHY1 | PHY2 | PHY3 |
75 + +--------+--------+--------+--------+
76 +
77 +$ref: ethernet-phy-package.yaml#
78 +
79 +properties:
80 + compatible:
81 + const: qcom,qca8084-package
82 +
83 + clocks:
84 + description: PHY package level initial common clocks, which are
85 + needed to be enabled after GPIO reset on the PHY package, these
86 + clocks are supplied from the PHY integrated clock controller
87 + (QCA8K-CC).
88 + items:
89 + - description: APB bridge clock
90 + - description: AHB clock
91 + - description: Security control clock
92 + - description: TLMM clock
93 + - description: TLMM AHB clock
94 + - description: CNOC AHB clock
95 + - description: MDIO AHB clock
96 +
97 + clock-names:
98 + items:
99 + - const: apb_bridge
100 + - const: ahb
101 + - const: sec_ctrl_ahb
102 + - const: tlmm
103 + - const: tlmm_ahb
104 + - const: cnoc_ahb
105 + - const: mdio_ahb
106 +
107 + resets:
108 + description: PHY package level initial common reset, which are
109 + needed to be deasserted after GPIO reset on the PHY package,
110 + this reset is provided by the PHY integrated clock controller
111 + to do PHY DSP reset.
112 + maxItems: 1
113 +
114 + qcom,package-mode:
115 + description: |
116 + The package mode of PHY supports to be configured as 3 modes
117 + to apply the combinations of interface mode of two PCSes
118 + correctly. This value should use one of the values defined in
119 + dt-bindings/net/qcom,qca808x.h. The package mode 10G-QXGMII of
120 + Quad PHY is used by default.
121 +
122 + package mode PCS1 PCS0
123 + phy mode (0) 10G-QXGMII for not used
124 + PHY0-PHY3
125 +
126 + switch mode (1) SGMII for SGMII for
127 + switch MAC0 switch MAC5 (optional)
128 +
129 + switch bypass MAC5 (2) SGMII for SGMII for
130 + switch MAC0 PHY3
131 + $ref: /schemas/types.yaml#/definitions/uint32
132 + enum: [0, 1, 2]
133 + default: 0
134 +
135 + qcom,phy-addr-fixup:
136 + description: MDIO address for PHY0-PHY3, PCS0 and PCS1 including
137 + PCS and XPCS, which can be optionally customized by programming
138 + the security control register of PHY package. The hardware default
139 + MDIO address of PHY0-PHY3, PCS0 and PCS1 including PCS and XPCS is
140 + 0-6.
141 + $ref: /schemas/types.yaml#/definitions/uint32-array
142 + minItems: 7
143 + maxItems: 7
144 +
145 +patternProperties:
146 + ^ethernet-phy(@[a-f0-9]+)?$:
147 + $ref: ethernet-phy.yaml#
148 +
149 + properties:
150 + compatible:
151 + const: ethernet-phy-id004d.d180
152 +
153 + required:
154 + - compatible
155 + - reg
156 + - clocks
157 + - resets
158 +
159 + unevaluatedProperties: false
160 +
161 +required:
162 + - compatible
163 + - clocks
164 + - clock-names
165 + - resets
166 +
167 +unevaluatedProperties: false
168 +
169 +examples:
170 + - |
171 + #include <dt-bindings/clock/qcom,qca8k-nsscc.h>
172 + #include <dt-bindings/net/qcom,qca808x.h>
173 + #include <dt-bindings/reset/qcom,qca8k-nsscc.h>
174 +
175 + mdio {
176 + #address-cells = <1>;
177 + #size-cells = <0>;
178 +
179 + ethernet-phy-package@1 {
180 + #address-cells = <1>;
181 + #size-cells = <0>;
182 + compatible = "qcom,qca8084-package";
183 + reg = <1>;
184 + clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>,
185 + <&qca8k_nsscc NSS_CC_AHB_CLK>,
186 + <&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>,
187 + <&qca8k_nsscc NSS_CC_TLMM_CLK>,
188 + <&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>,
189 + <&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>,
190 + <&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>;
191 + clock-names = "apb_bridge",
192 + "ahb",
193 + "sec_ctrl_ahb",
194 + "tlmm",
195 + "tlmm_ahb",
196 + "cnoc_ahb",
197 + "mdio_ahb";
198 + resets = <&qca8k_nsscc NSS_CC_GEPHY_FULL_ARES>;
199 + qcom,package-mode = <QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC>;
200 + qcom,phy-addr-fixup = <1 2 3 4 5 6 7>;
201 +
202 + ethernet-phy@1 {
203 + compatible = "ethernet-phy-id004d.d180";
204 + reg = <1>;
205 + clocks = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>;
206 + resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>;
207 + };
208 +
209 + ethernet-phy@2 {
210 + compatible = "ethernet-phy-id004d.d180";
211 + reg = <2>;
212 + clocks = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>;
213 + resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>;
214 + };
215 +
216 + ethernet-phy@3 {
217 + compatible = "ethernet-phy-id004d.d180";
218 + reg = <3>;
219 + clocks = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>;
220 + resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>;
221 + };
222 +
223 + ethernet-phy@4 {
224 + compatible = "ethernet-phy-id004d.d180";
225 + reg = <4>;
226 + clocks = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>;
227 + resets = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_ARES>;
228 + };
229 + };
230 + };
231 diff --git a/include/dt-bindings/net/qcom,qca808x.h b/include/dt-bindings/net/qcom,qca808x.h
232 new file mode 100644
233 index 000000000000..c3a2830445ea
234 --- /dev/null
235 +++ b/include/dt-bindings/net/qcom,qca808x.h
236 @@ -0,0 +1,14 @@
237 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
238 +/*
239 + * Device Tree constants for the Qualcomm QCA808X PHYs
240 + */
241 +
242 +#ifndef _DT_BINDINGS_QCOM_QCA808X_H
243 +#define _DT_BINDINGS_QCOM_QCA808X_H
244 +
245 +/* PHY package modes of QCA8084 to apply the interface modes of two PCSes. */
246 +#define QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED 0
247 +#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC 1
248 +#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_PHY 2
249 +
250 +#endif
251 --
252 2.45.2
253
Staging tree of Koen Vandeputte