git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 0bc16c6a8744a1c0293a31253020205b312895d3 Mon Sep 17 00:00:00 2001
   2 From: Tianling Shen <cnsztl@gmail.com>
   3 Date: Sat, 23 Dec 2023 12:00:07 +0800
   4 Subject: [PATCH] board: rockchip: Add support for FriendlyARM NanoPi R2C Plus
   5
   6 The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
   7 eMMC flash (8G) included.
   8
   9 The device tree is taken from the kernel v6.5.
  10
  11 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
  12 Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
  13 ---
  14  arch/arm/dts/Makefile                         |   1 +
  15  .../dts/rk3328-nanopi-r2c-plus-u-boot.dtsi    |   9 ++
  16  arch/arm/dts/rk3328-nanopi-r2c-plus.dts       |  33 +++++
  17  board/rockchip/evb_rk3328/MAINTAINERS         |   6 +
  18  configs/nanopi-r2c-plus-rk3328_defconfig      | 114 ++++++++++++++++++
  19  5 files changed, 163 insertions(+)
  20  create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
  21  create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus.dts
  22  create mode 100644 configs/nanopi-r2c-plus-rk3328_defconfig
  23
  24 --- a/arch/arm/dts/Makefile
  25 +++ b/arch/arm/dts/Makefile
  26 @@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
  27  dtb-$(CONFIG_ROCKCHIP_RK3328) += \
  28         rk3328-evb.dtb \
  29         rk3328-nanopi-r2c.dtb \
  30 +       rk3328-nanopi-r2c-plus.dtb \
  31         rk3328-nanopi-r2s.dtb \
  32         rk3328-orangepi-r1-plus.dtb \
  33         rk3328-orangepi-r1-plus-lts.dtb \
  34 --- /dev/null
  35 +++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
  36 @@ -0,0 +1,9 @@
  37 +// SPDX-License-Identifier: GPL-2.0-or-later
  38 +
  39 +#include "rk3328-nanopi-r2c-u-boot.dtsi"
  40 +
  41 +/ {
  42 +       chosen {
  43 +               u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
  44 +       };
  45 +};
  46 --- /dev/null
  47 +++ b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts
  48 @@ -0,0 +1,33 @@
  49 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  50 +/*
  51 + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
  52 + * (http://www.friendlyarm.com)
  53 + *
  54 + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
  55 + */
  56 +
  57 +/dts-v1/;
  58 +#include "rk3328-nanopi-r2c.dts"
  59 +
  60 +/ {
  61 +       model = "FriendlyElec NanoPi R2C Plus";
  62 +       compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
  63 +
  64 +       aliases {
  65 +               mmc1 = &emmc;
  66 +       };
  67 +};
  68 +
  69 +&emmc {
  70 +       bus-width = <8>;
  71 +       cap-mmc-highspeed;
  72 +       max-frequency = <150000000>;
  73 +       mmc-ddr-1_8v;
  74 +       mmc-hs200-1_8v;
  75 +       non-removable;
  76 +       pinctrl-names = "default";
  77 +       pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
  78 +       vmmc-supply = <&vcc_io_33>;
  79 +       vqmmc-supply = <&vcc18_emmc>;
  80 +       status = "okay";
  81 +};
  82 --- a/board/rockchip/evb_rk3328/MAINTAINERS
  83 +++ b/board/rockchip/evb_rk3328/MAINTAINERS
  84 @@ -11,6 +11,12 @@ S:      Maintained
  85  F:      configs/nanopi-r2c-rk3328_defconfig
  86  F:      arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
  87
  88 +NANOPI-R2C-PLUS-RK3328
  89 +M:      Tianling Shen <cnsztl@gmail.com>
  90 +S:      Maintained
  91 +F:      configs/nanopi-r2c-plus-rk3328_defconfig
  92 +F:      arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
  93 +
  94  NANOPI-R2S-RK3328
  95  M:      David Bauer <mail@david-bauer.net>
  96  S:      Maintained
  97 --- /dev/null
  98 +++ b/configs/nanopi-r2c-plus-rk3328_defconfig
  99 @@ -0,0 +1,114 @@
 100 +CONFIG_ARM=y
 101 +CONFIG_SKIP_LOWLEVEL_INIT=y
 102 +CONFIG_COUNTER_FREQUENCY=24000000
 103 +CONFIG_ARCH_ROCKCHIP=y
 104 +CONFIG_TEXT_BASE=0x00200000
 105 +CONFIG_SPL_GPIO=y
 106 +CONFIG_NR_DRAM_BANKS=1
 107 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 108 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
 109 +CONFIG_SF_DEFAULT_SPEED=20000000
 110 +CONFIG_ENV_OFFSET=0x3F8000
 111 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus"
 112 +CONFIG_DM_RESET=y
 113 +CONFIG_ROCKCHIP_RK3328=y
 114 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 115 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
 116 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
 117 +CONFIG_SPL_DRIVERS_MISC=y
 118 +CONFIG_SPL_STACK_R_ADDR=0x600000
 119 +CONFIG_SPL_STACK=0x400000
 120 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 121 +CONFIG_DEBUG_UART_BASE=0xFF130000
 122 +CONFIG_DEBUG_UART_CLOCK=24000000
 123 +CONFIG_SYS_LOAD_ADDR=0x800800
 124 +CONFIG_DEBUG_UART=y
 125 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 126 +CONFIG_FIT=y
 127 +CONFIG_FIT_VERBOSE=y
 128 +CONFIG_SPL_LOAD_FIT=y
 129 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
 130 +# CONFIG_DISPLAY_CPUINFO is not set
 131 +CONFIG_DISPLAY_BOARDINFO_LATE=y
 132 +CONFIG_MISC_INIT_R=y
 133 +CONFIG_SPL_MAX_SIZE=0x40000
 134 +CONFIG_SPL_PAD_TO=0x7f8000
 135 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 136 +CONFIG_SPL_BSS_START_ADDR=0x2000000
 137 +CONFIG_SPL_BSS_MAX_SIZE=0x2000
 138 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 139 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 140 +CONFIG_SPL_STACK_R=y
 141 +CONFIG_SPL_I2C=y
 142 +CONFIG_SPL_POWER=y
 143 +CONFIG_SPL_ATF=y
 144 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 145 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 146 +CONFIG_CMD_BOOTZ=y
 147 +CONFIG_CMD_GPT=y
 148 +CONFIG_CMD_MMC=y
 149 +CONFIG_CMD_USB=y
 150 +# CONFIG_CMD_SETEXPR is not set
 151 +CONFIG_CMD_TIME=y
 152 +CONFIG_SPL_OF_CONTROL=y
 153 +CONFIG_TPL_OF_CONTROL=y
 154 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 155 +CONFIG_TPL_OF_PLATDATA=y
 156 +CONFIG_ENV_IS_IN_MMC=y
 157 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 158 +CONFIG_SYS_MMC_ENV_DEV=1
 159 +CONFIG_NET_RANDOM_ETHADDR=y
 160 +CONFIG_TPL_DM=y
 161 +CONFIG_REGMAP=y
 162 +CONFIG_SPL_REGMAP=y
 163 +CONFIG_TPL_REGMAP=y
 164 +CONFIG_SYSCON=y
 165 +CONFIG_SPL_SYSCON=y
 166 +CONFIG_TPL_SYSCON=y
 167 +CONFIG_CLK=y
 168 +CONFIG_SPL_CLK=y
 169 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
 170 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 171 +CONFIG_ROCKCHIP_GPIO=y
 172 +CONFIG_SYS_I2C_ROCKCHIP=y
 173 +CONFIG_MISC=y
 174 +CONFIG_MMC_DW=y
 175 +CONFIG_MMC_DW_ROCKCHIP=y
 176 +CONFIG_ETH_DESIGNWARE=y
 177 +CONFIG_GMAC_ROCKCHIP=y
 178 +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 179 +CONFIG_PINCTRL=y
 180 +CONFIG_SPL_PINCTRL=y
 181 +CONFIG_DM_PMIC=y
 182 +CONFIG_PMIC_RK8XX=y
 183 +CONFIG_SPL_PMIC_RK8XX=y
 184 +CONFIG_SPL_DM_REGULATOR=y
 185 +CONFIG_REGULATOR_PWM=y
 186 +CONFIG_DM_REGULATOR_FIXED=y
 187 +CONFIG_SPL_DM_REGULATOR_FIXED=y
 188 +CONFIG_REGULATOR_RK8XX=y
 189 +CONFIG_PWM_ROCKCHIP=y
 190 +CONFIG_RAM=y
 191 +CONFIG_SPL_RAM=y
 192 +CONFIG_TPL_RAM=y
 193 +CONFIG_BAUDRATE=1500000
 194 +CONFIG_DEBUG_UART_SHIFT=2
 195 +CONFIG_SYS_NS16550_MEM32=y
 196 +CONFIG_SYSINFO=y
 197 +CONFIG_SYSRESET=y
 198 +# CONFIG_TPL_SYSRESET is not set
 199 +CONFIG_USB=y
 200 +CONFIG_USB_XHCI_HCD=y
 201 +CONFIG_USB_EHCI_HCD=y
 202 +CONFIG_USB_EHCI_GENERIC=y
 203 +CONFIG_USB_OHCI_HCD=y
 204 +CONFIG_USB_OHCI_GENERIC=y
 205 +CONFIG_USB_DWC2=y
 206 +CONFIG_USB_DWC3=y
 207 +# CONFIG_USB_DWC3_GADGET is not set
 208 +CONFIG_USB_DWC3_GENERIC=y
 209 +CONFIG_USB_GADGET=y
 210 +CONFIG_USB_GADGET_DWC2_OTG=y
 211 +CONFIG_SPL_TINY_MEMSET=y
 212 +CONFIG_TPL_TINY_MEMSET=y
 213 +CONFIG_ERRNO_STR=y