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1 From 2fc26b1b6377156e07c6c9ce934c58f634fcd21b Mon Sep 17 00:00:00 2001
2 From: Kuldeep Singh <kuldeep.singh@nxp.com>
3 Date: Wed, 1 Apr 2020 14:51:37 +0800
4 Subject: [PATCH] LF-18-3 spi: fsl-qspi: Allocate AHB memory dynamically for
5 imx platforms
6
7 LS platforms doesn't require dynamic allocaltion of AHB memory. So, let's
8 define a quirk which allocates AHB memory dynamically only for imx
9 platforms.
10
11 Fixes: c70adc97("spi: spi-fsl-qspi: dynamically alloc AHB memory for QSPI")
12 Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
13 [rebase]
14 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
15 ---
16 drivers/spi/spi-fsl-qspi.c | 71 +++++++++++++++++++++++++++++++++++-----------
17 1 file changed, 55 insertions(+), 16 deletions(-)
18
19 --- a/drivers/spi/spi-fsl-qspi.c
20 +++ b/drivers/spi/spi-fsl-qspi.c
21 @@ -197,6 +197,12 @@
22 */
23 #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
24
25 +/*
26 + * Use flash size for imx platforms and not for LS platforms. Define a
27 + * quirk which enables it only on imx platforms.
28 + */
29 +#define QUADSPI_QUIRK_USE_FLASH_SIZE BIT(6)
30 +
31 #define QUADSPI_MIN_IOMAP SZ_4M
32
33 struct fsl_qspi_devtype_data {
34 @@ -213,7 +219,7 @@ static const struct fsl_qspi_devtype_dat
35 .txfifo = SZ_64,
36 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
37 .ahb_buf_size = SZ_1K,
38 - .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
39 + .quirks = QUADSPI_QUIRK_SWAP_ENDIAN | QUADSPI_QUIRK_USE_FLASH_SIZE,
40 .little_endian = true,
41 };
42
43 @@ -222,7 +228,8 @@ static const struct fsl_qspi_devtype_dat
44 .txfifo = SZ_512,
45 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
46 .ahb_buf_size = SZ_1K,
47 - .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
48 + .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618 |
49 + QUADSPI_QUIRK_USE_FLASH_SIZE,
50 .little_endian = true,
51 };
52
53 @@ -232,7 +239,7 @@ static const struct fsl_qspi_devtype_dat
54 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
55 .ahb_buf_size = SZ_1K,
56 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
57 - QUADSPI_QUIRK_USE_TDH_SETTING,
58 + QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_USE_FLASH_SIZE,
59 .little_endian = true,
60 };
61
62 @@ -242,7 +249,7 @@ static const struct fsl_qspi_devtype_dat
63 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
64 .ahb_buf_size = SZ_1K,
65 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
66 - QUADSPI_QUIRK_USE_TDH_SETTING,
67 + QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_USE_FLASH_SIZE,
68 .little_endian = true,
69 };
70
71 @@ -310,6 +317,11 @@ static inline int needs_tdh_setting(stru
72 return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
73 }
74
75 +static inline int needs_flash_size(struct fsl_qspi *q)
76 +{
77 + return q->devtype_data->quirks & QUADSPI_QUIRK_USE_FLASH_SIZE;
78 +}
79 +
80 /*
81 * An IC bug makes it necessary to rearrange the 32-bit data.
82 * Later chips, such as IMX6SLX, have fixed this bug.
83 @@ -556,6 +568,14 @@ static void fsl_qspi_select_mem(struct f
84
85 static int fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
86 {
87 + if (!needs_flash_size(q)) {
88 + u32 size = q->devtype_data->ahb_buf_size;
89 + memcpy_fromio(op->data.buf.in,
90 + q->ahb_addr + q->selected * size,
91 + op->data.nbytes);
92 + return 0;
93 + }
94 +
95 u32 start = op->addr.val + q->selected * q->memmap_phy_size / 4;
96 u32 len = op->data.nbytes;
97
98 @@ -674,6 +694,7 @@ static int fsl_qspi_exec_op(struct spi_m
99 u32 addr_offset = 0;
100 int err = 0;
101 int invalid_mstrid = q->devtype_data->invalid_mstrid;
102 + u32 size = q->devtype_data->ahb_buf_size;
103
104 mutex_lock(&q->lock);
105
106 @@ -686,8 +707,11 @@ static int fsl_qspi_exec_op(struct spi_m
107 if (needs_amba_base_offset(q))
108 addr_offset = q->memmap_phy;
109
110 + if (needs_flash_size(q))
111 + size = q->memmap_phy_size / 4;
112 +
113 qspi_writel(q,
114 - q->selected * q->memmap_phy_size / 4 + addr_offset,
115 + q->selected * size + addr_offset,
116 base + QUADSPI_SFAR);
117
118 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
119 @@ -751,6 +775,7 @@ static int fsl_qspi_default_setup(struct
120 void __iomem *base = q->iobase;
121 u32 reg, addr_offset = 0;
122 int ret;
123 + u32 size = q->devtype_data->ahb_buf_size;
124
125 /* disable and unprepare clock to avoid glitch pass to controller */
126 fsl_qspi_clk_disable_unprep(q);
127 @@ -805,19 +830,22 @@ static int fsl_qspi_default_setup(struct
128 addr_offset = q->memmap_phy;
129
130 /*
131 - * In HW there can be a maximum of four chips on two buses with
132 - * two chip selects on each bus. We use four chip selects in SW
133 - * to differentiate between the four chips.
134 - * We divide the total memory region size equally for each chip
135 - * and set SFA1AD, SFA2AD, SFB1AD, SFB2AD accordingly.
136 + * In HW there can be a maximum of four chips on two buses with two
137 + * chip selects on each bus. We use four chip selects in SW to
138 + * differentiate between the four chips. We divide the total memory
139 + * region/ahb_buf_size size equally for each chip and set SFA1AD,
140 + * SFA2AD, SFB1AD, SFB2AD accordingly.
141 */
142 - qspi_writel(q, q->memmap_phy_size / 4 + addr_offset,
143 + if (needs_flash_size(q))
144 + size = q->memmap_phy_size / 4;
145 +
146 + qspi_writel(q, size + addr_offset,
147 base + QUADSPI_SFA1AD);
148 - qspi_writel(q, q->memmap_phy_size / 4 * 2 + addr_offset,
149 + qspi_writel(q, size * 2 + addr_offset,
150 base + QUADSPI_SFA2AD);
151 - qspi_writel(q, q->memmap_phy_size / 4 * 3 + addr_offset,
152 + qspi_writel(q, size * 3 + addr_offset,
153 base + QUADSPI_SFB1AD);
154 - qspi_writel(q, q->memmap_phy_size / 4 * 4 + addr_offset,
155 + qspi_writel(q, size * 4 + addr_offset,
156 base + QUADSPI_SFB2AD);
157
158 q->selected = -1;
159 @@ -904,6 +932,15 @@ static int fsl_qspi_probe(struct platfor
160
161 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
162 "QuadSPI-memory");
163 +
164 + if (!needs_flash_size(q)) {
165 + q->ahb_addr = devm_ioremap_resource(dev, res);
166 + if (IS_ERR(q->ahb_addr)) {
167 + ret = PTR_ERR(q->ahb_addr);
168 + goto err_put_ctrl;
169 + }
170 + }
171 +
172 q->memmap_phy = res->start;
173 q->memmap_phy_size = resource_size(res);
174
175 @@ -979,8 +1016,10 @@ static int fsl_qspi_remove(struct platfo
176
177 mutex_destroy(&q->lock);
178
179 - if (q->ahb_addr)
180 - iounmap(q->ahb_addr);
181 + if (needs_flash_size(q)) {
182 + if (q->ahb_addr)
183 + iounmap(q->ahb_addr);
184 + }
185
186 return 0;
187 }
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