git.openwrt.org Git - openwrt/staging/hauke.git/blob

   1 From 1b4638a9fa32d8a786e71a2a8813b2e1a3c15830 Mon Sep 17 00:00:00 2001
   2 From: Shengjiu Wang <shengjiu.wang@freescale.com>
   3 Date: Tue, 1 Aug 2017 16:10:38 +0800
   4 Subject: [PATCH] MLK-16130-1: ASoC: fsl_sai: enable TCE/RCE according to input
   5  channels
   6
   7 If there is only two channels input and slots is 2, then enable one
   8 port is enough for data transfer. so enable the TCE/RCE according to
   9 the input channels and slots configuration.
  10
  11 Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
  12 ---
  13  sound/soc/fsl/fsl_sai.c | 13 +++++++++++--
  14  1 file changed, 11 insertions(+), 2 deletions(-)
  15
  16 --- a/sound/soc/fsl/fsl_sai.c
  17 +++ b/sound/soc/fsl/fsl_sai.c
  18 @@ -487,11 +487,14 @@ static int fsl_sai_hw_params(struct snd_
  19         u32 val_cr4 = 0, val_cr5 = 0;
  20         u32 slots = (channels == 1) ? 2 : channels;
  21         u32 slot_width = word_width;
  22 +       u32 pins;
  23         int ret;
  24
  25         if (sai->slots)
  26                 slots = sai->slots;
  27
  28 +       pins = DIV_ROUND_UP(channels, slots);
  29 +
  30         if (sai->slot_width)
  31                 slot_width = sai->slot_width;
  32
  33 @@ -558,6 +561,10 @@ static int fsl_sai_hw_params(struct snd_
  34                                 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
  35         }
  36
  37 +       regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset),
  38 +                          FSL_SAI_CR3_TRCE_MASK,
  39 +                          FSL_SAI_CR3_TRCE((sai->dataline[tx] & ((1 << pins) - 1))));
  40 +
  41         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset),
  42                            FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
  43                            val_cr4);
  44 @@ -573,8 +580,12 @@ static int fsl_sai_hw_free(struct snd_pc
  45                 struct snd_soc_dai *cpu_dai)
  46  {
  47         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  48 +       unsigned char offset = sai->soc->reg_offset;
  49         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  50
  51 +       regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset),
  52 +                                  FSL_SAI_CR3_TRCE_MASK, 0);
  53 +
  54         if (!sai->slave_mode[tx] &&
  55                         sai->mclk_streams & BIT(substream->stream)) {
  56                 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
  57 @@ -694,7 +705,6 @@ static int fsl_sai_startup(struct snd_pc
  58                 struct snd_soc_dai *cpu_dai)
  59  {
  60         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  61 -       unsigned char offset = sai->soc->reg_offset;
  62         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  63         int ret;
  64
  65 @@ -724,7 +734,6 @@ static void fsl_sai_shutdown(struct snd_
  66                 struct snd_soc_dai *cpu_dai)
  67  {
  68         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  69 -       unsigned char offset = sai->soc->reg_offset;
  70         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  71
  72         regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);