2510ec327c4dfb75365d62de839757c3f27fd49a
[openwrt/staging/stintel.git] /
1 From d9b391e7b695b7de04c4363b5ec9ffaaed387353 Mon Sep 17 00:00:00 2001
2 From: Luo Jie <quic_luoj@quicinc.com>
3 Date: Wed, 8 Nov 2023 18:01:14 +0800
4 Subject: [PATCH 04/50] net: phy: qca808x: Add link_change_notify function for
5 QCA8084
6
7 When the link is changed, QCA8084 needs to do the fifo reset and
8 adjust the IPG level for the 10G-QXGMII link on the speed 1000M.
9
10 Change-Id: I21de802c78496fb95f1c5119fe3894c9fdebbd65
11 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
12 ---
13 drivers/net/phy/qcom/qca808x.c | 52 ++++++++++++++++++++++++++++++++++
14 1 file changed, 52 insertions(+)
15
16 diff --git a/drivers/net/phy/qcom/qca808x.c b/drivers/net/phy/qcom/qca808x.c
17 index c88fa59d4029..029d5f9de6b8 100644
18 --- a/drivers/net/phy/qcom/qca808x.c
19 +++ b/drivers/net/phy/qcom/qca808x.c
20 @@ -103,6 +103,14 @@
21 #define QCA8084_MSE_THRESHOLD 0x800a
22 #define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6
23
24 +/* QCA8084 FIFO reset control */
25 +#define QCA8084_FIFO_CONTROL 0x19
26 +#define QCA8084_FIFO_MAC_2_PHY BIT(1)
27 +#define QCA8084_FIFO_PHY_2_MAC BIT(0)
28 +
29 +#define QCA8084_MMD7_IPG_OP 0x901d
30 +#define QCA8084_IPG_10_TO_11_EN BIT(0)
31 +
32 MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
33 MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
34 MODULE_LICENSE("GPL");
35 @@ -697,6 +705,49 @@ static int qca8084_config_init(struct phy_device *phydev)
36 QCA8084_MSE_THRESHOLD_2P5G_VAL);
37 }
38
39 +static void qca8084_link_change_notify(struct phy_device *phydev)
40 +{
41 + int ret;
42 +
43 + /* Assert the FIFO between PHY and MAC. */
44 + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL,
45 + QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC,
46 + 0);
47 + if (ret) {
48 + phydev_err(phydev, "Asserting PHY FIFO failed\n");
49 + return;
50 + }
51 +
52 + /* If the PHY is in 10G_QXGMII mode, the FIFO needs to be kept in
53 + * reset state when link is down, otherwise the FIFO needs to be
54 + * de-asserted after waiting 50 ms to make the assert completed.
55 + */
56 + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII ||
57 + phydev->link) {
58 + msleep(50);
59 +
60 + /* Deassert the FIFO between PHY and MAC. */
61 + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL,
62 + QCA8084_FIFO_MAC_2_PHY |
63 + QCA8084_FIFO_PHY_2_MAC,
64 + QCA8084_FIFO_MAC_2_PHY |
65 + QCA8084_FIFO_PHY_2_MAC);
66 + if (ret) {
67 + phydev_err(phydev, "De-asserting PHY FIFO failed\n");
68 + return;
69 + }
70 + }
71 +
72 + /* Enable IPG level 10 to 11 tuning for link speed 1000M in the
73 + * 10G_QXGMII mode.
74 + */
75 + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
76 + phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP,
77 + QCA8084_IPG_10_TO_11_EN,
78 + phydev->speed == SPEED_1000 ?
79 + QCA8084_IPG_10_TO_11_EN : 0);
80 +}
81 +
82 static struct phy_driver qca808x_driver[] = {
83 {
84 /* Qualcomm QCA8081 */
85 @@ -746,6 +797,7 @@ static struct phy_driver qca808x_driver[] = {
86 .cable_test_start = qca808x_cable_test_start,
87 .cable_test_get_status = qca808x_cable_test_get_status,
88 .config_init = qca8084_config_init,
89 + .link_change_notify = qca8084_link_change_notify,
90 }, };
91
92 module_phy_driver(qca808x_driver);
93 --
94 2.45.2
95