1 From 80f4f866d7dad41b12cf37476c38766a89b8b5c4 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
3 Date: Fri, 1 Mar 2024 12:42:59 +0200
4 Subject: [PATCH 21/30] net: dsa: mt7530: do not use SW_PHY_RST to reset MT7531
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
10 According to the document MT7531 Reference Manual for Development Board
11 v1.0, the SW_PHY_RST bit on the SYS_CTRL register doesn't exist for
12 MT7531. This is likely why forcing link down on all ports is necessary for
15 Therefore, do not set SW_PHY_RST on mt7531_setup().
17 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
18 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
20 drivers/net/dsa/mt7530.c | 6 ++----
21 1 file changed, 2 insertions(+), 4 deletions(-)
23 --- a/drivers/net/dsa/mt7530.c
24 +++ b/drivers/net/dsa/mt7530.c
25 @@ -2487,14 +2487,12 @@ mt7531_setup(struct dsa_switch *ds)
26 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
27 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
29 - /* all MACs must be forced link-down before sw reset */
30 + /* Force link down on all ports before internal reset */
31 for (i = 0; i < MT7530_NUM_PORTS; i++)
32 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
34 /* Reset the switch through internal reset */
35 - mt7530_write(priv, MT7530_SYS_CTRL,
36 - SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
38 + mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
40 if (!priv->p5_sgmii) {
41 mt7531_pll_setup(priv);