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1 From 865433df5d11aef7cfe5d51b362b6276bddb7a15 Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Fri, 2 Aug 2019 17:45:56 +0800
4 Subject: [PATCH] i2c: imx: support slave mode for imx I2C driver
5
6 The patch supports slave mode for imx I2C driver
7
8 Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
9 Signed-off-by: Biwen Li <biwen.li@nxp.com>
10 ---
11 drivers/i2c/busses/i2c-imx.c | 219 +++++++++++++++++++++++++++++++++++++++----
12 1 file changed, 201 insertions(+), 18 deletions(-)
13
14 --- a/drivers/i2c/busses/i2c-imx.c
15 +++ b/drivers/i2c/busses/i2c-imx.c
16 @@ -265,6 +265,9 @@ struct imx_i2c_struct {
17 int pmuxcr_set;
18 int pmuxcr_endian;
19 void __iomem *pmuxcr_addr;
20 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
21 + struct i2c_client *slave;
22 +#endif
23 };
24
25 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
26 @@ -357,6 +360,14 @@ static inline unsigned char imx_i2c_read
27 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
28 }
29
30 +/* Set up i2c controller register and i2c status register to default value. */
31 +static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
32 +{
33 + imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
34 + i2c_imx, IMX_I2C_I2CR);
35 + imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
36 +}
37 +
38 /* Functions for DMA support */
39 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
40 dma_addr_t phy_addr)
41 @@ -681,23 +692,33 @@ static void i2c_imx_stop(struct imx_i2c_
42 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
43 }
44
45 -static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
46 +/* Clear interrupt flag bit */
47 +static void i2c_imx_clr_if_bit(unsigned int status, struct imx_i2c_struct *i2c_imx)
48 {
49 - struct imx_i2c_struct *i2c_imx = dev_id;
50 - unsigned int temp;
51 + status &= ~I2SR_IIF;
52 + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
53 + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
54 +}
55
56 - temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
57 - if (temp & I2SR_IIF) {
58 - /* save status register */
59 - i2c_imx->i2csr = temp;
60 - temp &= ~I2SR_IIF;
61 - temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
62 - imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
63 - wake_up(&i2c_imx->queue);
64 - return IRQ_HANDLED;
65 - }
66 +/* Clear arbitration lost bit */
67 +static void i2c_imx_clr_al_bit(unsigned int status, struct imx_i2c_struct *i2c_imx)
68 +{
69 + status &= ~I2SR_IAL;
70 + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
71 + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
72 +}
73
74 - return IRQ_NONE;
75 +static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx)
76 +{
77 + unsigned int status;
78 +
79 + /* Save status register */
80 + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
81 + i2c_imx->i2csr = status | I2SR_IIF;
82 +
83 + wake_up(&i2c_imx->queue);
84 +
85 + return IRQ_HANDLED;
86 }
87
88 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
89 @@ -1066,6 +1087,13 @@ static int i2c_imx_xfer(struct i2c_adapt
90
91 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
92
93 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
94 + if (i2c_imx->slave) {
95 + dev_err(&i2c_imx->adapter.dev, "Please not do operations of master mode in slave mode");
96 + return -EBUSY;
97 + }
98 +#endif
99 +
100 if (!pm_runtime_enabled(i2c_imx->adapter.dev.parent)) {
101 pm_runtime_enable(i2c_imx->adapter.dev.parent);
102 enable_runtime_pm = true;
103 @@ -1279,11 +1307,169 @@ static u32 i2c_imx_func(struct i2c_adapt
104 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
105 }
106
107 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
108 +static int i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
109 +{
110 + int temp;
111 +
112 + /* Resume */
113 + temp = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
114 + if (temp < 0) {
115 + dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
116 + return temp;
117 + }
118 +
119 + /* Set slave addr. */
120 + imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
121 +
122 + i2c_imx_reset_regs(i2c_imx);
123 +
124 + /* Enable module */
125 + temp = i2c_imx->hwdata->i2cr_ien_opcode;
126 + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
127 +
128 + /* Enable interrupt from i2c module */
129 + temp |= I2CR_IIEN;
130 + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
131 +
132 + /* Wait controller to be stable */
133 + usleep_range(50, 150);
134 + return 0;
135 +}
136 +
137 +static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx)
138 +{
139 + unsigned int status, ctl;
140 + u8 value;
141 +
142 + if (!i2c_imx->slave) {
143 + dev_err(&i2c_imx->adapter.dev, "cannot deal with slave irq,i2c_imx->slave is null");
144 + return IRQ_NONE;
145 + }
146 +
147 + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
148 + ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
149 + if (status & I2SR_IAL) { /* Arbitration lost */
150 + i2c_imx_clr_al_bit(status, i2c_imx);
151 + } else if (status & I2SR_IAAS) { /* Addressed as a slave */
152 + if (status & I2SR_SRW) { /* Master wants to read from us*/
153 + dev_dbg(&i2c_imx->adapter.dev, "read requested");
154 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_REQUESTED, &value);
155 +
156 + /* Slave transmit */
157 + ctl |= I2CR_MTX;
158 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
159 +
160 + /* Send data */
161 + imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
162 + } else { /* Master wants to write to us */
163 + dev_dbg(&i2c_imx->adapter.dev, "write requested");
164 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
165 +
166 + /* Slave receive */
167 + ctl &= ~I2CR_MTX;
168 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
169 + /* Dummy read */
170 + imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
171 + }
172 + } else if (!(ctl & I2CR_MTX)) { /* Receive mode */
173 + if (status & I2SR_IBB) { /* No STOP signal detected */
174 + ctl &= ~I2CR_MTX;
175 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
176 +
177 + value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
178 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
179 + } else { /* STOP signal is detected */
180 + dev_dbg(&i2c_imx->adapter.dev,
181 + "STOP signal detected");
182 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value);
183 + }
184 + } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
185 + ctl |= I2CR_MTX;
186 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
187 +
188 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_PROCESSED, &value);
189 +
190 + imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
191 + } else { /* Transmit mode received NAK */
192 + ctl &= ~I2CR_MTX;
193 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
194 + imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
195 + }
196 + return IRQ_HANDLED;
197 +}
198 +
199 +static int i2c_imx_reg_slave(struct i2c_client *client)
200 +{
201 + struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
202 + int ret;
203 + if (i2c_imx->slave)
204 + return -EBUSY;
205 +
206 + i2c_imx->slave = client;
207 +
208 + ret = i2c_imx_slave_init(i2c_imx);
209 + if (ret < 0)
210 + dev_err(&i2c_imx->adapter.dev, "failed to switch to slave mode");
211 +
212 + return ret;
213 +}
214 +
215 +static int i2c_imx_unreg_slave(struct i2c_client *client)
216 +{
217 + struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
218 + int ret;
219 +
220 + if (!i2c_imx->slave)
221 + return -EINVAL;
222 +
223 + /* Reset slave address. */
224 + imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
225 +
226 + i2c_imx_reset_regs(i2c_imx);
227 +
228 + i2c_imx->slave = NULL;
229 +
230 + /* Suspend */
231 + ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
232 + if (ret < 0)
233 + dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
234 +
235 + return ret;
236 +}
237 +#endif
238 +
239 static const struct i2c_algorithm i2c_imx_algo = {
240 .master_xfer = i2c_imx_xfer,
241 .functionality = i2c_imx_func,
242 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
243 + .reg_slave = i2c_imx_reg_slave,
244 + .unreg_slave = i2c_imx_unreg_slave,
245 +#endif
246 };
247
248 +static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
249 +{
250 + struct imx_i2c_struct *i2c_imx = dev_id;
251 + unsigned int status, ctl;
252 + irqreturn_t irq_status = IRQ_NONE;
253 +
254 + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
255 + ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
256 +
257 + if (status & I2SR_IIF) {
258 + i2c_imx_clr_if_bit(status, i2c_imx);
259 + if (ctl & I2CR_MSTA)
260 + irq_status = i2c_imx_master_isr(i2c_imx);
261 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
262 + else
263 + irq_status = i2c_imx_slave_isr(i2c_imx);
264 +#endif
265 + }
266 +
267 + return irq_status;
268 +}
269 +
270 static int i2c_imx_probe(struct platform_device *pdev)
271 {
272 struct imx_i2c_struct *i2c_imx;
273 @@ -1392,10 +1578,7 @@ static int i2c_imx_probe(struct platform
274 if (is_imx7d_i2c(i2c_imx) && i2c_imx->bitrate > IMX_I2C_MAX_E_BIT_RATE)
275 i2c_imx->bitrate = IMX_I2C_MAX_E_BIT_RATE;
276
277 - /* Set up chip registers to defaults */
278 - imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
279 - i2c_imx, IMX_I2C_I2CR);
280 - imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
281 + i2c_imx_reset_regs(i2c_imx);
282
283 /* Init optional bus recovery */
284 if (of_match_node(pinmux_of_match, pdev->dev.of_node))
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