git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 0d2351dc2768061689abd4de1529fa206bbd574e Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Thu, 27 Oct 2022 14:10:58 +0100
   4 Subject: [PATCH 04/10] net: mtk_eth_soc: convert mtk_sgmii to use
   5  regmap_update_bits()
   6
   7 mtk_sgmii does a lot of read-modify-write operations, for which there
   8 is a specific regmap function. Use this function instead of open-coding
   9 the operations.
  10
  11 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  13 ---
  14  drivers/net/ethernet/mediatek/mtk_sgmii.c | 61 ++++++++++-------------
  15  1 file changed, 26 insertions(+), 35 deletions(-)
  16
  17 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  18 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  19 @@ -36,23 +36,18 @@ static void mtk_pcs_get_state(struct phy
  20  /* For SGMII interface mode */
  21  static void mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
  22  {
  23 -       unsigned int val;
  24 -
  25         /* Setup the link timer and QPHY power up inside SGMIISYS */
  26         regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
  27                      SGMII_LINK_TIMER_DEFAULT);
  28
  29 -       regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
  30 -       val |= SGMII_REMOTE_FAULT_DIS;
  31 -       regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  32 -
  33 -       regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
  34 -       val |= SGMII_AN_RESTART;
  35 -       regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
  36 -
  37 -       regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
  38 -       val &= ~SGMII_PHYA_PWD;
  39 -       regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
  40 +       regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
  41 +                          SGMII_REMOTE_FAULT_DIS, SGMII_REMOTE_FAULT_DIS);
  42 +
  43 +       regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
  44 +                          SGMII_AN_RESTART, SGMII_AN_RESTART);
  45 +
  46 +       regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
  47 +                          SGMII_PHYA_PWD, 0);
  48  }
  49
  50  /* For 1000BASE-X and 2500BASE-X interface modes, which operate at a
  51 @@ -61,29 +56,26 @@ static void mtk_pcs_setup_mode_an(struct
  52  static void mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
  53                                      phy_interface_t interface)
  54  {
  55 -       unsigned int val;
  56 +       unsigned int rgc3;
  57
  58 -       regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
  59 -       val &= ~RG_PHY_SPEED_MASK;
  60         if (interface == PHY_INTERFACE_MODE_2500BASEX)
  61 -               val |= RG_PHY_SPEED_3_125G;
  62 -       regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
  63 +               rgc3 = RG_PHY_SPEED_3_125G;
  64 +
  65 +       regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
  66 +                          RG_PHY_SPEED_3_125G, rgc3);
  67
  68         /* Disable SGMII AN */
  69 -       regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
  70 -       val &= ~SGMII_AN_ENABLE;
  71 -       regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
  72 +       regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
  73 +                          SGMII_AN_ENABLE, 0);
  74
  75         /* Set the speed etc but leave the duplex unchanged */
  76 -       regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
  77 -       val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
  78 -       val |= SGMII_SPEED_1000;
  79 -       regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  80 +       regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
  81 +                          SGMII_IF_MODE_MASK & ~SGMII_DUPLEX_FULL,
  82 +                          SGMII_SPEED_1000);
  83
  84         /* Release PHYA power down state */
  85 -       regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
  86 -       val &= ~SGMII_PHYA_PWD;
  87 -       regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
  88 +       regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
  89 +                          SGMII_PHYA_PWD, 0);
  90  }
  91
  92  static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
  93 @@ -105,29 +97,28 @@ static int mtk_pcs_config(struct phylink
  94  static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
  95  {
  96         struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
  97 -       unsigned int val;
  98
  99 -       regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
 100 -       val |= SGMII_AN_RESTART;
 101 -       regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
 102 +       regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
 103 +                          SGMII_AN_RESTART, SGMII_AN_RESTART);
 104  }
 105
 106  static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
 107                             phy_interface_t interface, int speed, int duplex)
 108  {
 109         struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
 110 -       unsigned int val;
 111 +       unsigned int sgm_mode;
 112
 113         if (!phy_interface_mode_is_8023z(interface))
 114                 return;
 115
 116         /* SGMII force duplex setting */
 117 -       regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
 118 -       val &= ~SGMII_DUPLEX_FULL;
 119         if (duplex == DUPLEX_FULL)
 120 -               val |= SGMII_DUPLEX_FULL;
 121 +               sgm_mode = SGMII_DUPLEX_FULL;
 122 +       else
 123 +               sgm_mode = 0;
 124
 125 -       regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
 126 +       regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
 127 +                          SGMII_DUPLEX_FULL, sgm_mode);
 128  }
 129
 130  static const struct phylink_pcs_ops mtk_pcs_ops = {