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1 From 3d21ebe0b870b9b65b3be0c1473e7148256c4d16 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
3 Date: Tue, 24 Sep 2019 14:56:48 +0300
4 Subject: [PATCH] MLKU-114-1 crypto: caam - reduce page 0 regs access to
5 minimum
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 TODO:
11
12 1. if of_property_read_u32_index(,,index=0,) is to be used,
13 DT bindings (fsl-sec4.txt) should be updated to mandate for
14 -checked that all existing DTs are configured like this
15 -this might create problems in the future, if DTs are needed where
16 JR DT nodes would exist without the controller DT node
17 (directly on simple bus etc.)
18
19 2. MCFGR (ctrl->mcr)
20 How to determine caam_ptr_sz if MCFGR is not accesible?
21
22 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
23 ---
24 drivers/crypto/caam/caamalg.c | 21 ++++++------
25 drivers/crypto/caam/caamhash.c | 8 +++--
26 drivers/crypto/caam/caampkc.c | 4 +--
27 drivers/crypto/caam/caamrng.c | 4 +--
28 drivers/crypto/caam/ctrl.c | 78 ++++++++++++++++++++++++++----------------
29 5 files changed, 68 insertions(+), 47 deletions(-)
30
31 --- a/drivers/crypto/caam/caamalg.c
32 +++ b/drivers/crypto/caam/caamalg.c
33 @@ -3542,13 +3542,14 @@ int caam_algapi_init(struct device *ctrl
34 * First, detect presence and attributes of DES, AES, and MD blocks.
35 */
36 if (priv->era < 10) {
37 + struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon;
38 u32 cha_vid, cha_inst, aes_rn;
39
40 - cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
41 + cha_vid = rd_reg32(&perfmon->cha_id_ls);
42 aes_vid = cha_vid & CHA_ID_LS_AES_MASK;
43 md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
44
45 - cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
46 + cha_inst = rd_reg32(&perfmon->cha_num_ls);
47 des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >>
48 CHA_ID_LS_DES_SHIFT;
49 aes_inst = cha_inst & CHA_ID_LS_AES_MASK;
50 @@ -3558,24 +3559,24 @@ int caam_algapi_init(struct device *ctrl
51 ccha_inst = 0;
52 ptha_inst = 0;
53
54 - aes_rn = rd_reg32(&priv->ctrl->perfmon.cha_rev_ls) &
55 - CHA_ID_LS_AES_MASK;
56 + aes_rn = rd_reg32(&perfmon->cha_rev_ls) & CHA_ID_LS_AES_MASK;
57 gcm_support = !(aes_vid == CHA_VER_VID_AES_LP && aes_rn < 8);
58 } else {
59 + struct version_regs __iomem *vreg = &priv->jr[0]->vreg;
60 u32 aesa, mdha;
61
62 - aesa = rd_reg32(&priv->ctrl->vreg.aesa);
63 - mdha = rd_reg32(&priv->ctrl->vreg.mdha);
64 + aesa = rd_reg32(&vreg->aesa);
65 + mdha = rd_reg32(&vreg->mdha);
66
67 aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
68 md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
69
70 - des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;
71 + des_inst = rd_reg32(&vreg->desa) & CHA_VER_NUM_MASK;
72 aes_inst = aesa & CHA_VER_NUM_MASK;
73 md_inst = mdha & CHA_VER_NUM_MASK;
74 - ccha_inst = rd_reg32(&priv->ctrl->vreg.ccha) & CHA_VER_NUM_MASK;
75 - ptha_inst = rd_reg32(&priv->ctrl->vreg.ptha) & CHA_VER_NUM_MASK;
76 - arc4_inst = rd_reg32(&priv->ctrl->vreg.afha) & CHA_VER_NUM_MASK;
77 + ccha_inst = rd_reg32(&vreg->ccha) & CHA_VER_NUM_MASK;
78 + ptha_inst = rd_reg32(&vreg->ptha) & CHA_VER_NUM_MASK;
79 + arc4_inst = rd_reg32(&vreg->afha) & CHA_VER_NUM_MASK;
80
81 gcm_support = aesa & CHA_VER_MISC_AES_GCM;
82 }
83 --- a/drivers/crypto/caam/caamhash.c
84 +++ b/drivers/crypto/caam/caamhash.c
85 @@ -1991,12 +1991,14 @@ int caam_algapi_hash_init(struct device
86 * presence and attributes of MD block.
87 */
88 if (priv->era < 10) {
89 - md_vid = (rd_reg32(&priv->ctrl->perfmon.cha_id_ls) &
90 + struct caam_perfmon __iomem *perfmon = &priv->jr[0]->perfmon;
91 +
92 + md_vid = (rd_reg32(&perfmon->cha_id_ls) &
93 CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
94 - md_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
95 + md_inst = (rd_reg32(&perfmon->cha_num_ls) &
96 CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
97 } else {
98 - u32 mdha = rd_reg32(&priv->ctrl->vreg.mdha);
99 + u32 mdha = rd_reg32(&priv->jr[0]->vreg.mdha);
100
101 md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
102 md_inst = mdha & CHA_VER_NUM_MASK;
103 --- a/drivers/crypto/caam/caampkc.c
104 +++ b/drivers/crypto/caam/caampkc.c
105 @@ -1099,10 +1099,10 @@ int caam_pkc_init(struct device *ctrldev
106
107 /* Determine public key hardware accelerator presence. */
108 if (priv->era < 10)
109 - pk_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
110 + pk_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
111 CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT;
112 else
113 - pk_inst = rd_reg32(&priv->ctrl->vreg.pkha) & CHA_VER_NUM_MASK;
114 + pk_inst = rd_reg32(&priv->jr[0]->vreg.pkha) & CHA_VER_NUM_MASK;
115
116 /* Do not register algorithms if PKHA is not present. */
117 if (!pk_inst)
118 --- a/drivers/crypto/caam/caamrng.c
119 +++ b/drivers/crypto/caam/caamrng.c
120 @@ -363,10 +363,10 @@ int caam_rng_init(struct device *ctrldev
121
122 /* Check for an instantiated RNG before registration */
123 if (priv->era < 10)
124 - rng_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
125 + rng_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
126 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
127 else
128 - rng_inst = rd_reg32(&priv->ctrl->vreg.rng) & CHA_VER_NUM_MASK;
129 + rng_inst = rd_reg32(&priv->jr[0]->vreg.rng) & CHA_VER_NUM_MASK;
130
131 if (!rng_inst)
132 return 0;
133 --- a/drivers/crypto/caam/ctrl.c
134 +++ b/drivers/crypto/caam/ctrl.c
135 @@ -379,7 +379,7 @@ start_rng:
136 RTMCTL_SAMP_MODE_RAW_ES_SC);
137 }
138
139 -static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
140 +static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon)
141 {
142 static const struct {
143 u16 ip_id;
144 @@ -405,12 +405,12 @@ static int caam_get_era_from_hw(struct c
145 u16 ip_id;
146 int i;
147
148 - ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
149 + ccbvid = rd_reg32(&perfmon->ccb_id);
150 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
151 if (era) /* This is '0' prior to CAAM ERA-6 */
152 return era;
153
154 - id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
155 + id_ms = rd_reg32(&perfmon->caam_id_ms);
156 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
157 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
158
159 @@ -428,7 +428,7 @@ static int caam_get_era_from_hw(struct c
160 * In case this property is not passed an attempt to retrieve the CAAM
161 * era via register reads will be made.
162 **/
163 -static int caam_get_era(struct caam_ctrl __iomem *ctrl)
164 +static int caam_get_era(struct caam_perfmon __iomem *perfmon)
165 {
166 struct device_node *caam_node;
167 int ret;
168 @@ -441,7 +441,7 @@ static int caam_get_era(struct caam_ctrl
169 if (!ret)
170 return prop;
171 else
172 - return caam_get_era_from_hw(ctrl);
173 + return caam_get_era_from_hw(perfmon);
174 }
175
176 /*
177 @@ -575,8 +575,8 @@ static int caam_probe(struct platform_de
178 struct device_node *nprop, *np;
179 struct caam_ctrl __iomem *ctrl;
180 struct caam_drv_private *ctrlpriv;
181 + struct caam_perfmon __iomem *perfmon;
182 #ifdef CONFIG_DEBUG_FS
183 - struct caam_perfmon *perfmon;
184 struct dentry *dfs_root;
185 #endif
186 u32 scfgr, comp_params;
187 @@ -616,9 +616,36 @@ static int caam_probe(struct platform_de
188 return ret;
189 }
190
191 - caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
192 + ring = 0;
193 + for_each_available_child_of_node(nprop, np)
194 + if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
195 + of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
196 + u32 reg;
197 +
198 + if (of_property_read_u32_index(np, "reg", 0, &reg)) {
199 + dev_err(dev, "%s read reg property error\n",
200 + np->full_name);
201 + continue;
202 + }
203 +
204 + ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
205 + ((__force uint8_t *)ctrl + reg);
206 +
207 + ctrlpriv->total_jobrs++;
208 + ring++;
209 + }
210 +
211 + /*
212 + * Wherever possible, instead of accessing registers from the global page,
213 + * use the alias registers in the first (cf. DT nodes order)
214 + * job ring's page.
215 + */
216 + perfmon = ring ? (struct caam_perfmon *)&ctrlpriv->jr[0]->perfmon :
217 + (struct caam_perfmon *)&ctrl->perfmon;
218 +
219 + caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
220 (CSTA_PLEND | CSTA_ALT_PLEND));
221 - comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
222 + comp_params = rd_reg32(&perfmon->comp_parms_ms);
223 if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
224 caam_ptr_sz = sizeof(u64);
225 else
226 @@ -718,7 +745,7 @@ static int caam_probe(struct platform_de
227 return ret;
228 }
229
230 - ctrlpriv->era = caam_get_era(ctrl);
231 + ctrlpriv->era = caam_get_era(perfmon);
232 ctrlpriv->domain = iommu_get_domain_for_dev(dev);
233
234 #ifdef CONFIG_DEBUG_FS
235 @@ -727,8 +754,6 @@ static int caam_probe(struct platform_de
236 * "caam" and nprop->full_name. The OF name isn't distinctive,
237 * but does separate instances
238 */
239 - perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
240 -
241 dfs_root = debugfs_create_dir(dev_name(dev), NULL);
242 ret = devm_add_action_or_reset(dev, caam_remove_debugfs, dfs_root);
243 if (ret)
244 @@ -754,31 +779,24 @@ static int caam_probe(struct platform_de
245 #endif
246 }
247
248 - ring = 0;
249 - for_each_available_child_of_node(nprop, np)
250 - if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
251 - of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
252 - ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
253 - ((__force uint8_t *)ctrl +
254 - (ring + JR_BLOCK_NUMBER) *
255 - BLOCK_OFFSET
256 - );
257 - ctrlpriv->total_jobrs++;
258 - ring++;
259 - }
260 -
261 /* If no QI and no rings specified, quit and go home */
262 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
263 dev_err(dev, "no queues configured, terminating\n");
264 return -ENOMEM;
265 }
266
267 - if (ctrlpriv->era < 10)
268 - rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &
269 + if (ctrlpriv->era < 10) {
270 + rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
271 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
272 - else
273 - rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
274 + } else {
275 + struct version_regs __iomem *vreg;
276 +
277 + vreg = ring ? (struct version_regs *)&ctrlpriv->jr[0]->vreg :
278 + (struct version_regs *)&ctrl->vreg;
279 +
280 + rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>
281 CHA_VER_VID_SHIFT;
282 + }
283
284 /*
285 * If SEC has RNG version >= 4 and RNG state handle has not been
286 @@ -847,8 +865,8 @@ static int caam_probe(struct platform_de
287
288 /* NOTE: RTIC detection ought to go here, around Si time */
289
290 - caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
291 - (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
292 + caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
293 + (u64)rd_reg32(&perfmon->caam_id_ls);
294
295 /* Report "alive" for developer to see */
296 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
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