235daca71c863e6e6618271cd2802b6338ca9fa7
[openwrt/staging/svanheule.git] /
1 From f5db8274c8d6c86812fd2036ae49153d3ade3eaa Mon Sep 17 00:00:00 2001
2 From: richard zhu <hongxing.zhu@nxp.com>
3 Date: Wed, 6 Nov 2019 15:11:36 +0800
4 Subject: [PATCH] PCI: dwc: fix the msi failure after pm operations
5
6 The controller may be powered off (Link is in L3) during the suspend
7 mode. The MSI_ADDR would be missed after resume and MSI function
8 would be failed.
9 Re-store MSI_ADDR to fix the MSI failure after PM operations.
10
11 Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
12 Acked-by: Fugang Duan <fugang.duan@nxp.com>
13 Acked-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
14 ---
15 drivers/pci/controller/dwc/pcie-designware-host.c | 6 ++++++
16 1 file changed, 6 insertions(+)
17
18 --- a/drivers/pci/controller/dwc/pcie-designware-host.c
19 +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
20 @@ -654,6 +654,12 @@ void dw_pcie_setup_rc(struct pcie_port *
21 dw_pcie_setup(pci);
22
23 if (!pp->ops->msi_host_init) {
24 + /* Program the msi_data */
25 + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
26 + lower_32_bits((u64)pp->msi_data));
27 + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
28 + upper_32_bits((u64)pp->msi_data));
29 +
30 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
31
32 /* Initialize IRQ Status array */