git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From c1619d9de2da093a585426e9cef353ca1789236d Mon Sep 17 00:00:00 2001
   2 From: Florinel Iordache <florinel.iordache@nxp.com>
   3 Date: Mon, 5 Nov 2018 17:02:19 +0200
   4 Subject: [PATCH] arm64: dts: lx2160: PCS PHY definitions for 10GBase-KR and
   5  40GBase-KR backplane modes
   6
   7 Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
   8 ---
   9  arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 40 +++++++++++++++++++++++
  10  1 file changed, 40 insertions(+)
  11
  12 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
  13 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
  14 @@ -162,3 +162,43 @@
  15  &usb1 {
  16         status = "okay";
  17  };
  18 +
  19 +&pcs_mdio1 {
  20 +       pcs_phy1: ethernet-phy@0 {
  21 +               compatible = "ethernet-phy-ieee802.3-c45";
  22 +               backplane-mode = "40gbase-kr";
  23 +               reg = <0x0>;
  24 +               fsl,lane-handle = <&serdes1>;
  25 +               fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */
  26 +       };
  27 +};
  28 +
  29 +&pcs_mdio2 {
  30 +       pcs_phy2: ethernet-phy@0 {
  31 +               compatible = "ethernet-phy-ieee802.3-c45";
  32 +               backplane-mode = "40gbase-kr";
  33 +               reg = <0x0>;
  34 +               fsl,lane-handle = <&serdes1>;
  35 +               fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */
  36 +       };
  37 +};
  38 +
  39 +&pcs_mdio3 {
  40 +       pcs_phy3: ethernet-phy@0 {
  41 +               compatible = "ethernet-phy-ieee802.3-c45";
  42 +               backplane-mode = "10gbase-kr";
  43 +               reg = <0x0>;
  44 +               fsl,lane-handle = <&serdes1>;
  45 +               fsl,lane-reg = <0xF00 0x100>; /* lane H */
  46 +       };
  47 +};
  48 +
  49 +&pcs_mdio4 {
  50 +       pcs_phy4: ethernet-phy@0 {
  51 +               compatible = "ethernet-phy-ieee802.3-c45";
  52 +               backplane-mode = "10gbase-kr";
  53 +               reg = <0x0>;
  54 +               fsl,lane-handle = <&serdes1>;
  55 +               fsl,lane-reg = <0xE00 0x100>; /* lane G */
  56 +       };
  57 +};