git.openwrt.org Git - openwrt/staging/rmilecki.git/blob

   1 From 489aea123d74a846ce746bfdb3efe1e7ad512e0d Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Tue, 22 Aug 2023 17:31:24 +0100
   4 Subject: [PATCH 110/250] net: ethernet: mtk_eth_soc: fix register definitions
   5  for MT7988
   6
   7 More register macros need to be adjusted for the 3rd GMAC on MT7988.
   8 Account for added bit in SYSCFG0_SGMII_MASK.
   9
  10 Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 Reviewed-by: Simon Horman <horms@kernel.org>
  13 Link: https://lore.kernel.org/r/1c8da012e2ca80939906d85f314138c552139f0f.1692721443.git.daniel@makrotopia.org
  14 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  15 ---
  16  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++---
  17  1 file changed, 5 insertions(+), 3 deletions(-)
  18
  19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  21 @@ -133,10 +133,12 @@
  22  #define MTK_GDMA_XGDM_SEL      BIT(31)
  23
  24  /* Unicast Filter MAC Address Register - Low */
  25 -#define MTK_GDMA_MAC_ADRL(x)   (0x508 + (x * 0x1000))
  26 +#define MTK_GDMA_MAC_ADRL(x)   ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?   \
  27 +                                  0x548 : 0x508 + (_x * 0x1000); })
  28
  29  /* Unicast Filter MAC Address Register - High */
  30 -#define MTK_GDMA_MAC_ADRH(x)   (0x50C + (x * 0x1000))
  31 +#define MTK_GDMA_MAC_ADRH(x)   ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?   \
  32 +                                  0x54C : 0x50C + (_x * 0x1000); })
  33
  34  /* FE global misc reg*/
  35  #define MTK_FE_GLO_MISC         0x124
  36 @@ -503,7 +505,7 @@
  37  #define ETHSYS_SYSCFG0         0x14
  38  #define SYSCFG0_GE_MASK                0x3
  39  #define SYSCFG0_GE_MODE(x, y)  (x << (12 + (y * 2)))
  40 -#define SYSCFG0_SGMII_MASK     GENMASK(9, 8)
  41 +#define SYSCFG0_SGMII_MASK     GENMASK(9, 7)
  42  #define SYSCFG0_SGMII_GMAC1    ((2 << 8) & SYSCFG0_SGMII_MASK)
  43  #define SYSCFG0_SGMII_GMAC2    ((3 << 8) & SYSCFG0_SGMII_MASK)
  44  #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)