git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 66307f9e693bd4822a683fac8cf1f63533822c18 Mon Sep 17 00:00:00 2001
   2 From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
   3 Date: Thu, 3 May 2018 18:05:43 +0300
   4 Subject: [PATCH] arm64: dts: ls104xa: set mask to drop TBU ID from StreamID
   5
   6 The StreamID entering the SMMU is actually a concatenation of the
   7 SMMU TBU ID and the ICID configured in software.
   8 Since the TBU ID is internal to the SoC and since we want that the
   9 actual the ICID configured in software to enter the SMMU witout any
  10 additional set bits, mask out the TBU ID bits and leave only the
  11 relevant ICID bits to enter SMMU.
  12
  13 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
  14 ---
  15  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
  16  arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
  17  2 files changed, 2 insertions(+)
  18
  19 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
  20 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
  21 @@ -230,6 +230,7 @@
  22                         compatible = "arm,mmu-500";
  23                         reg = <0 0x9000000 0 0x400000>;
  24                         dma-coherent;
  25 +                       stream-match-mask = <0x7f00>;
  26                         #global-interrupts = <2>;
  27                         #iommu-cells = <1>;
  28                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  29 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
  30 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
  31 @@ -233,6 +233,7 @@
  32                         compatible = "arm,mmu-500";
  33                         reg = <0 0x9000000 0 0x400000>;
  34                         dma-coherent;
  35 +                       stream-match-mask = <0x7f00>;
  36                         #global-interrupts = <2>;
  37                         #iommu-cells = <1>;
  38                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,