1fe7e255b71edf55e4b868a595bf43b21d2e7e96
[openwrt/staging/stintel.git] /
1 From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001
2 From: Balsam CHIHI <bchihi@baylibre.com>
3 Date: Tue, 17 Oct 2023 21:05:43 +0200
4 Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192
5 support
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 Add LVTS Driver support for MT8192.
11
12 Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
13 Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
14 Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
15 Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
16 [bero@baylibre.com: cosmetic changes, rebase]
17 Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
18 Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
19 Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
20 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
21 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
22 Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com
23 ---
24 drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
25 1 file changed, 95 insertions(+)
26
27 --- a/drivers/thermal/mediatek/lvts_thermal.c
28 +++ b/drivers/thermal/mediatek/lvts_thermal.c
29 @@ -92,6 +92,7 @@
30 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
31
32 #define LVTS_HW_SHUTDOWN_MT7988 105000
33 +#define LVTS_HW_SHUTDOWN_MT8192 105000
34 #define LVTS_HW_SHUTDOWN_MT8195 105000
35
36 #define LVTS_MINIMUM_THRESHOLD 20000
37 @@ -1331,6 +1332,88 @@ static int lvts_resume(struct device *de
38 return 0;
39 }
40
41 +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
42 + {
43 + .cal_offset = { 0x04, 0x08 },
44 + .lvts_sensor = {
45 + { .dt_id = MT8192_MCU_BIG_CPU0 },
46 + { .dt_id = MT8192_MCU_BIG_CPU1 }
47 + },
48 + .num_lvts_sensor = 2,
49 + .offset = 0x0,
50 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
51 + .mode = LVTS_MSR_FILTERED_MODE,
52 + },
53 + {
54 + .cal_offset = { 0x0c, 0x10 },
55 + .lvts_sensor = {
56 + { .dt_id = MT8192_MCU_BIG_CPU2 },
57 + { .dt_id = MT8192_MCU_BIG_CPU3 }
58 + },
59 + .num_lvts_sensor = 2,
60 + .offset = 0x100,
61 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
62 + .mode = LVTS_MSR_FILTERED_MODE,
63 + },
64 + {
65 + .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
66 + .lvts_sensor = {
67 + { .dt_id = MT8192_MCU_LITTLE_CPU0 },
68 + { .dt_id = MT8192_MCU_LITTLE_CPU1 },
69 + { .dt_id = MT8192_MCU_LITTLE_CPU2 },
70 + { .dt_id = MT8192_MCU_LITTLE_CPU3 }
71 + },
72 + .num_lvts_sensor = 4,
73 + .offset = 0x200,
74 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
75 + .mode = LVTS_MSR_FILTERED_MODE,
76 + }
77 +};
78 +
79 +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
80 + {
81 + .cal_offset = { 0x24, 0x28 },
82 + .lvts_sensor = {
83 + { .dt_id = MT8192_AP_VPU0 },
84 + { .dt_id = MT8192_AP_VPU1 }
85 + },
86 + .num_lvts_sensor = 2,
87 + .offset = 0x0,
88 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
89 + },
90 + {
91 + .cal_offset = { 0x2c, 0x30 },
92 + .lvts_sensor = {
93 + { .dt_id = MT8192_AP_GPU0 },
94 + { .dt_id = MT8192_AP_GPU1 }
95 + },
96 + .num_lvts_sensor = 2,
97 + .offset = 0x100,
98 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
99 + },
100 + {
101 + .cal_offset = { 0x34, 0x38 },
102 + .lvts_sensor = {
103 + { .dt_id = MT8192_AP_INFRA },
104 + { .dt_id = MT8192_AP_CAM },
105 + },
106 + .num_lvts_sensor = 2,
107 + .offset = 0x200,
108 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
109 + },
110 + {
111 + .cal_offset = { 0x3c, 0x40, 0x44 },
112 + .lvts_sensor = {
113 + { .dt_id = MT8192_AP_MD0 },
114 + { .dt_id = MT8192_AP_MD1 },
115 + { .dt_id = MT8192_AP_MD2 }
116 + },
117 + .num_lvts_sensor = 3,
118 + .offset = 0x300,
119 + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
120 + }
121 +};
122 +
123 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
124 {
125 .cal_offset = { 0x04, 0x07 },
126 @@ -1417,6 +1500,16 @@ static const struct lvts_data mt7988_lvt
127 .temp_offset = LVTS_COEFF_B_MT7988,
128 };
129
130 +static const struct lvts_data mt8192_lvts_mcu_data = {
131 + .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
132 + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
133 +};
134 +
135 +static const struct lvts_data mt8192_lvts_ap_data = {
136 + .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
137 + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
138 +};
139 +
140 static const struct lvts_data mt8195_lvts_mcu_data = {
141 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
142 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
143 @@ -1433,6 +1526,8 @@ static const struct lvts_data mt8195_lvt
144
145 static const struct of_device_id lvts_of_match[] = {
146 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
147 + { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
148 + { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
149 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
150 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
151 {},