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1 From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
3 Date: Mon, 22 Apr 2024 10:15:13 +0300
4 Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and
5 MT7530_MHWTRAP
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531.
11 It's called hardware trap on MT7530, software trap on MT7531. That's
12 because some bits of the trap on MT7530 cannot be modified by software
13 whilst all bits of the trap on MT7531 can. Rename the definitions for them
14 to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the
15 definitions specific to the switch model.
16
17 Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ.
18
19 Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on
20 par with the "MT7621 Giga Switch Programming Guide v0.3" document.
21
22 Make an enumaration for the XTAL frequency. Set the data type of the xtal
23 variable on mt7531_pll_setup() to it.
24
25 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
26 ---
27 drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++--------------------
28 drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------
29 2 files changed, 54 insertions(+), 55 deletions(-)
30
31 --- a/drivers/net/dsa/mt7530.c
32 +++ b/drivers/net/dsa/mt7530.c
33 @@ -417,23 +417,23 @@ mt7530_setup_port6(struct dsa_switch *ds
34
35 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
36
37 - xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
38 + xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK;
39
40 - if (xtal == HWTRAP_XTAL_25MHZ)
41 + if (xtal == MT7530_XTAL_25MHZ)
42 ssc_delta = 0x57;
43 else
44 ssc_delta = 0x87;
45
46 if (priv->id == ID_MT7621) {
47 /* PLL frequency: 125MHz: 1.0GBit */
48 - if (xtal == HWTRAP_XTAL_40MHZ)
49 + if (xtal == MT7530_XTAL_40MHZ)
50 ncpo1 = 0x0640;
51 - if (xtal == HWTRAP_XTAL_25MHZ)
52 + if (xtal == MT7530_XTAL_25MHZ)
53 ncpo1 = 0x0a00;
54 } else { /* PLL frequency: 250MHz: 2.0Gbit */
55 - if (xtal == HWTRAP_XTAL_40MHZ)
56 + if (xtal == MT7530_XTAL_40MHZ)
57 ncpo1 = 0x0c80;
58 - if (xtal == HWTRAP_XTAL_25MHZ)
59 + if (xtal == MT7530_XTAL_25MHZ)
60 ncpo1 = 0x1400;
61 }
62
63 @@ -456,19 +456,20 @@ mt7530_setup_port6(struct dsa_switch *ds
64 static void
65 mt7531_pll_setup(struct mt7530_priv *priv)
66 {
67 + enum mt7531_xtal_fsel xtal;
68 u32 top_sig;
69 u32 hwstrap;
70 - u32 xtal;
71 u32 val;
72
73 val = mt7530_read(priv, MT7531_CREV);
74 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
75 - hwstrap = mt7530_read(priv, MT7531_HWTRAP);
76 + hwstrap = mt7530_read(priv, MT753X_TRAP);
77 if ((val & CHIP_REV_M) > 0)
78 - xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
79 - HWTRAP_XTAL_FSEL_25MHZ;
80 + xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :
81 + MT7531_XTAL_FSEL_25MHZ;
82 else
83 - xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
84 + xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ :
85 + MT7531_XTAL_FSEL_40MHZ;
86
87 /* Step 1 : Disable MT7531 COREPLL */
88 val = mt7530_read(priv, MT7531_PLLGP_EN);
89 @@ -497,13 +498,13 @@ mt7531_pll_setup(struct mt7530_priv *pri
90 usleep_range(25, 35);
91
92 switch (xtal) {
93 - case HWTRAP_XTAL_FSEL_25MHZ:
94 + case MT7531_XTAL_FSEL_25MHZ:
95 val = mt7530_read(priv, MT7531_PLLGP_CR0);
96 val &= ~RG_COREPLL_SDM_PCW_M;
97 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
98 mt7530_write(priv, MT7531_PLLGP_CR0, val);
99 break;
100 - case HWTRAP_XTAL_FSEL_40MHZ:
101 + case MT7531_XTAL_FSEL_40MHZ:
102 val = mt7530_read(priv, MT7531_PLLGP_CR0);
103 val &= ~RG_COREPLL_SDM_PCW_M;
104 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
105 @@ -877,20 +878,20 @@ static void mt7530_setup_port5(struct ds
106
107 mutex_lock(&priv->reg_mutex);
108
109 - val = mt7530_read(priv, MT7530_MHWTRAP);
110 + val = mt7530_read(priv, MT753X_MTRAP);
111
112 - val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
113 - val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
114 + val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
115 + val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
116
117 switch (priv->p5_mode) {
118 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
119 case MUX_PHY_P0:
120 - val |= MHWTRAP_PHY0_SEL;
121 + val |= MT7530_P5_PHY0_SEL;
122 fallthrough;
123
124 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
125 case MUX_PHY_P4:
126 - val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
127 + val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
128
129 /* Setup the MAC by default for the cpu port */
130 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
131 @@ -898,13 +899,13 @@ static void mt7530_setup_port5(struct ds
132
133 /* GMAC5: P5 -> SoC MAC or external PHY */
134 default:
135 - val &= ~MHWTRAP_P5_DIS;
136 + val &= ~MT7530_P5_DIS;
137 break;
138 }
139
140 /* Setup RGMII settings */
141 if (phy_interface_mode_is_rgmii(interface)) {
142 - val |= MHWTRAP_P5_RGMII_MODE;
143 + val |= MT7530_P5_RGMII_MODE;
144
145 /* P5 RGMII RX Clock Control: delay setting for 1000M */
146 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
147 @@ -924,7 +925,7 @@ static void mt7530_setup_port5(struct ds
148 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
149 }
150
151 - mt7530_write(priv, MT7530_MHWTRAP, val);
152 + mt7530_write(priv, MT753X_MTRAP, val);
153
154 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
155 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
156 @@ -2365,7 +2366,7 @@ mt7530_setup(struct dsa_switch *ds)
157 }
158
159 /* Waiting for MT7530 got to stable */
160 - INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
161 + INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
162 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
163 20, 1000000);
164 if (ret < 0) {
165 @@ -2380,7 +2381,7 @@ mt7530_setup(struct dsa_switch *ds)
166 return -ENODEV;
167 }
168
169 - if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
170 + if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) {
171 dev_err(priv->dev,
172 "MT7530 with a 20MHz XTAL is not supported!\n");
173 return -EINVAL;
174 @@ -2401,12 +2402,12 @@ mt7530_setup(struct dsa_switch *ds)
175 RD_TAP_MASK, RD_TAP(16));
176
177 /* Enable port 6 */
178 - val = mt7530_read(priv, MT7530_MHWTRAP);
179 - val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
180 - val |= MHWTRAP_MANUAL;
181 - mt7530_write(priv, MT7530_MHWTRAP, val);
182 + val = mt7530_read(priv, MT753X_MTRAP);
183 + val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
184 + val |= MT7530_CHG_TRAP;
185 + mt7530_write(priv, MT753X_MTRAP, val);
186
187 - if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
188 + if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
189 mt7530_pll_setup(priv);
190
191 mt753x_trap_frames(priv);
192 @@ -2586,7 +2587,7 @@ mt7531_setup(struct dsa_switch *ds)
193 }
194
195 /* Waiting for MT7530 got to stable */
196 - INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
197 + INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
198 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
199 20, 1000000);
200 if (ret < 0) {
201 --- a/drivers/net/dsa/mt7530.h
202 +++ b/drivers/net/dsa/mt7530.h
203 @@ -495,32 +495,30 @@ enum mt7531_clk_skew {
204 MT7531_CLK_SKEW_REVERSE = 3,
205 };
206
207 -/* Register for hw trap status */
208 -#define MT7530_HWTRAP 0x7800
209 -#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
210 -#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
211 -#define HWTRAP_XTAL_40MHZ (BIT(10))
212 -#define HWTRAP_XTAL_20MHZ (BIT(9))
213 +/* Register for trap status */
214 +#define MT753X_TRAP 0x7800
215 +#define MT7530_XTAL_MASK (BIT(10) | BIT(9))
216 +#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9))
217 +#define MT7530_XTAL_40MHZ BIT(10)
218 +#define MT7530_XTAL_20MHZ BIT(9)
219 +#define MT7531_XTAL25 BIT(7)
220
221 -#define MT7531_HWTRAP 0x7800
222 -#define HWTRAP_XTAL_FSEL_MASK BIT(7)
223 -#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
224 -#define HWTRAP_XTAL_FSEL_40MHZ 0
225 -/* Unique fields of (M)HWSTRAP for MT7531 */
226 -#define XTAL_FSEL_S 7
227 -#define XTAL_FSEL_M BIT(7)
228 -#define PHY_EN BIT(6)
229 -#define CHG_STRAP BIT(8)
230 +/* Register for trap modification */
231 +#define MT753X_MTRAP 0x7804
232 +#define MT7530_P5_PHY0_SEL BIT(20)
233 +#define MT7530_CHG_TRAP BIT(16)
234 +#define MT7530_P5_MAC_SEL BIT(13)
235 +#define MT7530_P6_DIS BIT(8)
236 +#define MT7530_P5_RGMII_MODE BIT(7)
237 +#define MT7530_P5_DIS BIT(6)
238 +#define MT7530_PHY_INDIRECT_ACCESS BIT(5)
239 +#define MT7531_CHG_STRAP BIT(8)
240 +#define MT7531_PHY_EN BIT(6)
241
242 -/* Register for hw trap modification */
243 -#define MT7530_MHWTRAP 0x7804
244 -#define MHWTRAP_PHY0_SEL BIT(20)
245 -#define MHWTRAP_MANUAL BIT(16)
246 -#define MHWTRAP_P5_MAC_SEL BIT(13)
247 -#define MHWTRAP_P6_DIS BIT(8)
248 -#define MHWTRAP_P5_RGMII_MODE BIT(7)
249 -#define MHWTRAP_P5_DIS BIT(6)
250 -#define MHWTRAP_PHY_ACCESS BIT(5)
251 +enum mt7531_xtal_fsel {
252 + MT7531_XTAL_FSEL_25MHZ,
253 + MT7531_XTAL_FSEL_40MHZ,
254 +};
255
256 /* Register for TOP signal control */
257 #define MT7530_TOP_SIG_CTRL 0x7808
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