git.openwrt.org Git - openwrt/staging/blogic.git/blob

   1 From d883a12a547b6d42e795ff3b5ac87cfd013b5423 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Thu, 7 Jul 2022 03:09:36 +0200
   4 Subject: [PATCH 2/8] ARM: dts: qcom: ipq8064: add gsbi6 missing definition
   5
   6 Add gsbi6 missing definition for ipq8064.
   7
   8 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
   9 Tested-by: Jonathan McDowell <noodles@earth.li>
  10 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  11 Link: https://lore.kernel.org/r/20220707010943.20857-3-ansuelsmth@gmail.com
  12 ---
  13  arch/arm/boot/dts/qcom-ipq8064.dtsi | 43 +++++++++++++++++++++++++++++
  14  1 file changed, 43 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  17 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  18 @@ -663,6 +663,49 @@
  19                         };
  20                 };
  21
  22 +               gsbi6: gsbi@16500000 {
  23 +                       compatible = "qcom,gsbi-v1.0.0";
  24 +                       reg = <0x16500000 0x100>;
  25 +                       cell-index = <6>;
  26 +                       clocks = <&gcc GSBI6_H_CLK>;
  27 +                       clock-names = "iface";
  28 +                       #address-cells = <1>;
  29 +                       #size-cells = <1>;
  30 +                       ranges;
  31 +
  32 +                       syscon-tcsr = <&tcsr>;
  33 +
  34 +                       status = "disabled";
  35 +
  36 +                       gsbi6_i2c: i2c@16580000 {
  37 +                               compatible = "qcom,i2c-qup-v1.1.1";
  38 +                               reg = <0x16580000 0x1000>;
  39 +                               interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  40 +
  41 +                               clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
  42 +                               clock-names = "core", "iface";
  43 +
  44 +                               #address-cells = <1>;
  45 +                               #size-cells = <0>;
  46 +
  47 +                               status = "disabled";
  48 +                       };
  49 +
  50 +                       gsbi6_spi: spi@16580000 {
  51 +                               compatible = "qcom,spi-qup-v1.1.1";
  52 +                               reg = <0x16580000 0x1000>;
  53 +                               interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  54 +
  55 +                               clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
  56 +                               clock-names = "core", "iface";
  57 +
  58 +                               #address-cells = <1>;
  59 +                               #size-cells = <0>;
  60 +
  61 +                               status = "disabled";
  62 +                       };
  63 +               };
  64 +
  65                 gsbi7: gsbi@16600000 {
  66                         status = "disabled";
  67                         compatible = "qcom,gsbi-v1.0.0";