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1 From 3d98604921d4b7216d3d0c8a76160dce083bd040 Mon Sep 17 00:00:00 2001
2 From: Devi Priya <quic_devipriy@quicinc.com>
3 Date: Fri, 25 Oct 2024 09:25:17 +0530
4 Subject: [PATCH 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset
5 definitions
6
7 Add NSSCC clock and reset definitions for ipq9574.
8
9 Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
10 Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
11 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12 ---
13 .../bindings/clock/qcom,ipq9574-nsscc.yaml | 73 +++++++++
14 .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 ++++++++++++++++++
15 .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +++++++++++++++
16 3 files changed, 359 insertions(+)
17 create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
18 create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
19 create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
20
21 diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
22 new file mode 100644
23 index 000000000000..14a320079dbf
24 --- /dev/null
25 +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
26 @@ -0,0 +1,73 @@
27 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
28 +%YAML 1.2
29 +---
30 +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
31 +$schema: http://devicetree.org/meta-schemas/core.yaml#
32 +
33 +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
34 +
35 +maintainers:
36 + - Bjorn Andersson <andersson@kernel.org>
37 + - Anusha Rao <quic_anusha@quicinc.com>
38 +
39 +description: |
40 + Qualcomm networking sub system clock control module provides the clocks,
41 + resets and power domains on IPQ9574
42 +
43 + See also::
44 + include/dt-bindings/clock/qcom,ipq9574-nsscc.h
45 + include/dt-bindings/reset/qcom,ipq9574-nsscc.h
46 +
47 +properties:
48 + compatible:
49 + const: qcom,ipq9574-nsscc
50 +
51 + clocks:
52 + items:
53 + - description: Board XO source
54 + - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
55 + - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
56 + - description: GCC GPLL0 OUT AUX clock source
57 + - description: Uniphy0 NSS Rx clock source
58 + - description: Uniphy0 NSS Tx clock source
59 + - description: Uniphy1 NSS Rx clock source
60 + - description: Uniphy1 NSS Tx clock source
61 + - description: Uniphy2 NSS Rx clock source
62 + - description: Uniphy2 NSS Tx clock source
63 + - description: GCC NSSCC clock source
64 +
65 + '#interconnect-cells':
66 + const: 1
67 +
68 +required:
69 + - compatible
70 + - clocks
71 +
72 +allOf:
73 + - $ref: qcom,gcc.yaml#
74 +
75 +unevaluatedProperties: false
76 +
77 +examples:
78 + - |
79 + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
80 + #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
81 + clock-controller@39b00000 {
82 + compatible = "qcom,ipq9574-nsscc";
83 + reg = <0x39b00000 0x80000>;
84 + clocks = <&xo_board_clk>,
85 + <&cmn_pll NSS_1200MHZ_CLK>,
86 + <&cmn_pll PPE_353MHZ_CLK>,
87 + <&gcc GPLL0_OUT_AUX>,
88 + <&uniphy 0>,
89 + <&uniphy 1>,
90 + <&uniphy 2>,
91 + <&uniphy 3>,
92 + <&uniphy 4>,
93 + <&uniphy 5>,
94 + <&gcc GCC_NSSCC_CLK>;
95 + #clock-cells = <1>;
96 + #reset-cells = <1>;
97 + #power-domain-cells = <1>;
98 + };
99 +...
100 diff --git a/include/dt-bindings/clock/qcom,ipq9574-nsscc.h b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h
101 new file mode 100644
102 index 000000000000..59d57d9c788c
103 --- /dev/null
104 +++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h
105 @@ -0,0 +1,152 @@
106 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
107 +/*
108 + * Copyright (c) 2023, The Linux Foundation. All rights reserved.
109 + */
110 +
111 +#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
112 +#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H
113 +
114 +#define NSS_CC_CE_APB_CLK 0
115 +#define NSS_CC_CE_AXI_CLK 1
116 +#define NSS_CC_CE_CLK_SRC 2
117 +#define NSS_CC_CFG_CLK_SRC 3
118 +#define NSS_CC_CLC_AXI_CLK 4
119 +#define NSS_CC_CLC_CLK_SRC 5
120 +#define NSS_CC_CRYPTO_CLK 6
121 +#define NSS_CC_CRYPTO_CLK_SRC 7
122 +#define NSS_CC_CRYPTO_PPE_CLK 8
123 +#define NSS_CC_HAQ_AHB_CLK 9
124 +#define NSS_CC_HAQ_AXI_CLK 10
125 +#define NSS_CC_HAQ_CLK_SRC 11
126 +#define NSS_CC_IMEM_AHB_CLK 12
127 +#define NSS_CC_IMEM_CLK_SRC 13
128 +#define NSS_CC_IMEM_QSB_CLK 14
129 +#define NSS_CC_INT_CFG_CLK_SRC 15
130 +#define NSS_CC_NSS_CSR_CLK 16
131 +#define NSS_CC_NSSNOC_CE_APB_CLK 17
132 +#define NSS_CC_NSSNOC_CE_AXI_CLK 18
133 +#define NSS_CC_NSSNOC_CLC_AXI_CLK 19
134 +#define NSS_CC_NSSNOC_CRYPTO_CLK 20
135 +#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21
136 +#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22
137 +#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23
138 +#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24
139 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 25
140 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 26
141 +#define NSS_CC_NSSNOC_PPE_CLK 27
142 +#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28
143 +#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29
144 +#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30
145 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31
146 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32
147 +#define NSS_CC_PORT1_MAC_CLK 33
148 +#define NSS_CC_PORT1_RX_CLK 34
149 +#define NSS_CC_PORT1_RX_CLK_SRC 35
150 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36
151 +#define NSS_CC_PORT1_TX_CLK 37
152 +#define NSS_CC_PORT1_TX_CLK_SRC 38
153 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39
154 +#define NSS_CC_PORT2_MAC_CLK 40
155 +#define NSS_CC_PORT2_RX_CLK 41
156 +#define NSS_CC_PORT2_RX_CLK_SRC 42
157 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43
158 +#define NSS_CC_PORT2_TX_CLK 44
159 +#define NSS_CC_PORT2_TX_CLK_SRC 45
160 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46
161 +#define NSS_CC_PORT3_MAC_CLK 47
162 +#define NSS_CC_PORT3_RX_CLK 48
163 +#define NSS_CC_PORT3_RX_CLK_SRC 49
164 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50
165 +#define NSS_CC_PORT3_TX_CLK 51
166 +#define NSS_CC_PORT3_TX_CLK_SRC 52
167 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53
168 +#define NSS_CC_PORT4_MAC_CLK 54
169 +#define NSS_CC_PORT4_RX_CLK 55
170 +#define NSS_CC_PORT4_RX_CLK_SRC 56
171 +#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57
172 +#define NSS_CC_PORT4_TX_CLK 58
173 +#define NSS_CC_PORT4_TX_CLK_SRC 59
174 +#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60
175 +#define NSS_CC_PORT5_MAC_CLK 61
176 +#define NSS_CC_PORT5_RX_CLK 62
177 +#define NSS_CC_PORT5_RX_CLK_SRC 63
178 +#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64
179 +#define NSS_CC_PORT5_TX_CLK 65
180 +#define NSS_CC_PORT5_TX_CLK_SRC 66
181 +#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67
182 +#define NSS_CC_PORT6_MAC_CLK 68
183 +#define NSS_CC_PORT6_RX_CLK 69
184 +#define NSS_CC_PORT6_RX_CLK_SRC 70
185 +#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71
186 +#define NSS_CC_PORT6_TX_CLK 72
187 +#define NSS_CC_PORT6_TX_CLK_SRC 73
188 +#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74
189 +#define NSS_CC_PPE_CLK_SRC 75
190 +#define NSS_CC_PPE_EDMA_CFG_CLK 76
191 +#define NSS_CC_PPE_EDMA_CLK 77
192 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 78
193 +#define NSS_CC_PPE_SWITCH_CFG_CLK 79
194 +#define NSS_CC_PPE_SWITCH_CLK 80
195 +#define NSS_CC_PPE_SWITCH_IPE_CLK 81
196 +#define NSS_CC_UBI0_CLK_SRC 82
197 +#define NSS_CC_UBI0_DIV_CLK_SRC 83
198 +#define NSS_CC_UBI1_CLK_SRC 84
199 +#define NSS_CC_UBI1_DIV_CLK_SRC 85
200 +#define NSS_CC_UBI2_CLK_SRC 86
201 +#define NSS_CC_UBI2_DIV_CLK_SRC 87
202 +#define NSS_CC_UBI32_AHB0_CLK 88
203 +#define NSS_CC_UBI32_AHB1_CLK 89
204 +#define NSS_CC_UBI32_AHB2_CLK 90
205 +#define NSS_CC_UBI32_AHB3_CLK 91
206 +#define NSS_CC_UBI32_AXI0_CLK 92
207 +#define NSS_CC_UBI32_AXI1_CLK 93
208 +#define NSS_CC_UBI32_AXI2_CLK 94
209 +#define NSS_CC_UBI32_AXI3_CLK 95
210 +#define NSS_CC_UBI32_CORE0_CLK 96
211 +#define NSS_CC_UBI32_CORE1_CLK 97
212 +#define NSS_CC_UBI32_CORE2_CLK 98
213 +#define NSS_CC_UBI32_CORE3_CLK 99
214 +#define NSS_CC_UBI32_INTR0_AHB_CLK 100
215 +#define NSS_CC_UBI32_INTR1_AHB_CLK 101
216 +#define NSS_CC_UBI32_INTR2_AHB_CLK 102
217 +#define NSS_CC_UBI32_INTR3_AHB_CLK 103
218 +#define NSS_CC_UBI32_NC_AXI0_CLK 104
219 +#define NSS_CC_UBI32_NC_AXI1_CLK 105
220 +#define NSS_CC_UBI32_NC_AXI2_CLK 106
221 +#define NSS_CC_UBI32_NC_AXI3_CLK 107
222 +#define NSS_CC_UBI32_UTCM0_CLK 108
223 +#define NSS_CC_UBI32_UTCM1_CLK 109
224 +#define NSS_CC_UBI32_UTCM2_CLK 110
225 +#define NSS_CC_UBI32_UTCM3_CLK 111
226 +#define NSS_CC_UBI3_CLK_SRC 112
227 +#define NSS_CC_UBI3_DIV_CLK_SRC 113
228 +#define NSS_CC_UBI_AXI_CLK_SRC 114
229 +#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115
230 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 116
231 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 117
232 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 118
233 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 119
234 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 120
235 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 121
236 +#define NSS_CC_UNIPHY_PORT4_RX_CLK 122
237 +#define NSS_CC_UNIPHY_PORT4_TX_CLK 123
238 +#define NSS_CC_UNIPHY_PORT5_RX_CLK 124
239 +#define NSS_CC_UNIPHY_PORT5_TX_CLK 125
240 +#define NSS_CC_UNIPHY_PORT6_RX_CLK 126
241 +#define NSS_CC_UNIPHY_PORT6_TX_CLK 127
242 +#define NSS_CC_XGMAC0_PTP_REF_CLK 128
243 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129
244 +#define NSS_CC_XGMAC1_PTP_REF_CLK 130
245 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131
246 +#define NSS_CC_XGMAC2_PTP_REF_CLK 132
247 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133
248 +#define NSS_CC_XGMAC3_PTP_REF_CLK 134
249 +#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135
250 +#define NSS_CC_XGMAC4_PTP_REF_CLK 136
251 +#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137
252 +#define NSS_CC_XGMAC5_PTP_REF_CLK 138
253 +#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139
254 +#define UBI32_PLL 140
255 +#define UBI32_PLL_MAIN 141
256 +
257 +#endif
258 diff --git a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h
259 new file mode 100644
260 index 000000000000..6910db0cff51
261 --- /dev/null
262 +++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h
263 @@ -0,0 +1,134 @@
264 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
265 +/*
266 + * Copyright (c) 2023, The Linux Foundation. All rights reserved.
267 + */
268 +
269 +#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
270 +#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
271 +
272 +#define EDMA_HW_RESET 0
273 +#define NSS_CC_CE_BCR 1
274 +#define NSS_CC_CLC_BCR 2
275 +#define NSS_CC_EIP197_BCR 3
276 +#define NSS_CC_HAQ_BCR 4
277 +#define NSS_CC_IMEM_BCR 5
278 +#define NSS_CC_MAC_BCR 6
279 +#define NSS_CC_PPE_BCR 7
280 +#define NSS_CC_UBI_BCR 8
281 +#define NSS_CC_UNIPHY_BCR 9
282 +#define UBI3_CLKRST_CLAMP_ENABLE 10
283 +#define UBI3_CORE_CLAMP_ENABLE 11
284 +#define UBI2_CLKRST_CLAMP_ENABLE 12
285 +#define UBI2_CORE_CLAMP_ENABLE 13
286 +#define UBI1_CLKRST_CLAMP_ENABLE 14
287 +#define UBI1_CORE_CLAMP_ENABLE 15
288 +#define UBI0_CLKRST_CLAMP_ENABLE 16
289 +#define UBI0_CORE_CLAMP_ENABLE 17
290 +#define NSSNOC_NSS_CSR_ARES 18
291 +#define NSS_CSR_ARES 19
292 +#define PPE_BTQ_ARES 20
293 +#define PPE_IPE_ARES 21
294 +#define PPE_ARES 22
295 +#define PPE_CFG_ARES 23
296 +#define PPE_EDMA_ARES 24
297 +#define PPE_EDMA_CFG_ARES 25
298 +#define CRY_PPE_ARES 26
299 +#define NSSNOC_PPE_ARES 27
300 +#define NSSNOC_PPE_CFG_ARES 28
301 +#define PORT1_MAC_ARES 29
302 +#define PORT2_MAC_ARES 30
303 +#define PORT3_MAC_ARES 31
304 +#define PORT4_MAC_ARES 32
305 +#define PORT5_MAC_ARES 33
306 +#define PORT6_MAC_ARES 34
307 +#define XGMAC0_PTP_REF_ARES 35
308 +#define XGMAC1_PTP_REF_ARES 36
309 +#define XGMAC2_PTP_REF_ARES 37
310 +#define XGMAC3_PTP_REF_ARES 38
311 +#define XGMAC4_PTP_REF_ARES 39
312 +#define XGMAC5_PTP_REF_ARES 40
313 +#define HAQ_AHB_ARES 41
314 +#define HAQ_AXI_ARES 42
315 +#define NSSNOC_HAQ_AHB_ARES 43
316 +#define NSSNOC_HAQ_AXI_ARES 44
317 +#define CE_APB_ARES 45
318 +#define CE_AXI_ARES 46
319 +#define NSSNOC_CE_APB_ARES 47
320 +#define NSSNOC_CE_AXI_ARES 48
321 +#define CRYPTO_ARES 49
322 +#define NSSNOC_CRYPTO_ARES 50
323 +#define NSSNOC_NC_AXI0_1_ARES 51
324 +#define UBI0_CORE_ARES 52
325 +#define UBI1_CORE_ARES 53
326 +#define UBI2_CORE_ARES 54
327 +#define UBI3_CORE_ARES 55
328 +#define NC_AXI0_ARES 56
329 +#define UTCM0_ARES 57
330 +#define NC_AXI1_ARES 58
331 +#define UTCM1_ARES 59
332 +#define NC_AXI2_ARES 60
333 +#define UTCM2_ARES 61
334 +#define NC_AXI3_ARES 62
335 +#define UTCM3_ARES 63
336 +#define NSSNOC_NC_AXI0_ARES 64
337 +#define AHB0_ARES 65
338 +#define INTR0_AHB_ARES 66
339 +#define AHB1_ARES 67
340 +#define INTR1_AHB_ARES 68
341 +#define AHB2_ARES 69
342 +#define INTR2_AHB_ARES 70
343 +#define AHB3_ARES 71
344 +#define INTR3_AHB_ARES 72
345 +#define NSSNOC_AHB0_ARES 73
346 +#define NSSNOC_INT0_AHB_ARES 74
347 +#define AXI0_ARES 75
348 +#define AXI1_ARES 76
349 +#define AXI2_ARES 77
350 +#define AXI3_ARES 78
351 +#define NSSNOC_AXI0_ARES 79
352 +#define IMEM_QSB_ARES 80
353 +#define NSSNOC_IMEM_QSB_ARES 81
354 +#define IMEM_AHB_ARES 82
355 +#define NSSNOC_IMEM_AHB_ARES 83
356 +#define UNIPHY_PORT1_RX_ARES 84
357 +#define UNIPHY_PORT1_TX_ARES 85
358 +#define UNIPHY_PORT2_RX_ARES 86
359 +#define UNIPHY_PORT2_TX_ARES 87
360 +#define UNIPHY_PORT3_RX_ARES 88
361 +#define UNIPHY_PORT3_TX_ARES 89
362 +#define UNIPHY_PORT4_RX_ARES 90
363 +#define UNIPHY_PORT4_TX_ARES 91
364 +#define UNIPHY_PORT5_RX_ARES 92
365 +#define UNIPHY_PORT5_TX_ARES 93
366 +#define UNIPHY_PORT6_RX_ARES 94
367 +#define UNIPHY_PORT6_TX_ARES 95
368 +#define PORT1_RX_ARES 96
369 +#define PORT1_TX_ARES 97
370 +#define PORT2_RX_ARES 98
371 +#define PORT2_TX_ARES 99
372 +#define PORT3_RX_ARES 100
373 +#define PORT3_TX_ARES 101
374 +#define PORT4_RX_ARES 102
375 +#define PORT4_TX_ARES 103
376 +#define PORT5_RX_ARES 104
377 +#define PORT5_TX_ARES 105
378 +#define PORT6_RX_ARES 106
379 +#define PORT6_TX_ARES 107
380 +#define PPE_FULL_RESET 108
381 +#define UNIPHY0_SOFT_RESET 109
382 +#define UNIPHY1_SOFT_RESET 110
383 +#define UNIPHY2_SOFT_RESET 111
384 +#define UNIPHY_PORT1_ARES 112
385 +#define UNIPHY_PORT2_ARES 113
386 +#define UNIPHY_PORT3_ARES 114
387 +#define UNIPHY_PORT4_ARES 115
388 +#define UNIPHY_PORT5_ARES 116
389 +#define UNIPHY_PORT6_ARES 117
390 +#define NSSPORT1_RESET 118
391 +#define NSSPORT2_RESET 119
392 +#define NSSPORT3_RESET 120
393 +#define NSSPORT4_RESET 121
394 +#define NSSPORT5_RESET 122
395 +#define NSSPORT6_RESET 123
396 +
397 +#endif
398 --
399 2.45.2
400
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