git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From 060265cd3cec354804c0c944e42de83cec9f2f2a Mon Sep 17 00:00:00 2001
   2 From: Mihai Serban <mihai.serban@nxp.com>
   3 Date: Fri, 21 Apr 2017 15:57:58 +0300
   4 Subject: [PATCH] MLK-14847: Revert "ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI
   5  master mode"
   6
   7 This reverts commit c768ed336bba ("ASoC: fsl-sai: set xCR4/xCR5/xMR for
   8 SAI master mode")
   9
  10 This change was already introduced by commit 51659ca069ce ("ASoC: fsl-sai:
  11 set xCR4/xCR5/xMR for SAI master mode") from upstream.
  12
  13 Manually adjust the code to match the changes introduced by subsequent
  14 commit b2936555bb38 ("MLK-13609: ASoC: fsl_sai: fix for synchronize mode")
  15 by removing updates to FSL_SAI_TMR/FSL_SAI_RMR registers.
  16
  17 Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
  18 ---
  19  sound/soc/fsl/fsl_sai.c | 29 -----------------------------
  20  1 file changed, 29 deletions(-)
  21
  22 --- a/sound/soc/fsl/fsl_sai.c
  23 +++ b/sound/soc/fsl/fsl_sai.c
  24 @@ -507,35 +507,6 @@ static int fsl_sai_hw_params(struct snd_
  25                         regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
  26                                 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
  27                                 FSL_SAI_CR5_FBT_MASK, val_cr5);
  28 -                       regmap_write(sai->regmap, FSL_SAI_TMR,
  29 -                               ~0UL - ((1 << channels) - 1));
  30 -               } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
  31 -                       regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
  32 -                               FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
  33 -                               val_cr4);
  34 -                       regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
  35 -                               FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
  36 -                               FSL_SAI_CR5_FBT_MASK, val_cr5);
  37 -                       regmap_write(sai->regmap, FSL_SAI_RMR,
  38 -                               ~0UL - ((1 << channels) - 1));
  39 -               }
  40 -       }
  41 -
  42 -       /*
  43 -        * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
  44 -        * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
  45 -        * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
  46 -        * error.
  47 -        */
  48 -
  49 -       if (!sai->slave_mode[tx]) {
  50 -               if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
  51 -                       regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
  52 -                               FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
  53 -                               val_cr4);
  54 -                       regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
  55 -                               FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
  56 -                               FSL_SAI_CR5_FBT_MASK, val_cr5);
  57                 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
  58                         regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
  59                                 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,