1 From 5ebee96094c5a97a89a986108242cca9d853ff55 Mon Sep 17 00:00:00 2001
2 From: Roy Pledge <roy.pledge@nxp.com>
3 Date: Wed, 27 Sep 2017 14:50:08 -0400
4 Subject: [PATCH] staging/fsl_qbman: Calculate valid bit from MC-RR
6 Use the management commmand response registers to determine
7 the next expected valid bit when initializing a software
8 portal. This avoids using the wrong valid bit in cases
9 where a command was partially written but then not
12 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
14 drivers/staging/fsl_qbman/qman_low.h | 19 +++++++++++++++++--
15 1 file changed, 17 insertions(+), 2 deletions(-)
17 --- a/drivers/staging/fsl_qbman/qman_low.h
18 +++ b/drivers/staging/fsl_qbman/qman_low.h
19 @@ -1095,11 +1095,26 @@ static inline void qm_mr_set_ithresh(str
21 static inline int qm_mc_init(struct qm_portal *portal)
24 register struct qm_mc *mc = &portal->mc;
26 mc->cr = portal->addr.addr_ce + QM_CL_CR;
27 mc->rr = portal->addr.addr_ce + QM_CL_RR0;
28 - mc->rridx = (__raw_readb(&mc->cr->__dont_write_directly__verb) &
29 - QM_MCC_VERB_VBIT) ? 0 : 1;
32 + * The expected valid bit polarity for the next CR command is 0
33 + * if RR1 contains a valid response, and is 1 if RR0 contains a
34 + * valid response. If both RR contain all 0, this indicates either
35 + * that no command has been executed since reset (in which case the
36 + * expected valid bit polarity is 1)
38 + rr0 = __raw_readb(&mc->rr->verb);
39 + rr1 = __raw_readb(&(mc->rr+1)->verb);
40 + if ((rr0 == 0 && rr1 == 0) || rr0 != 0)
45 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
46 #ifdef CONFIG_FSL_DPA_CHECKING
47 mc->state = qman_mc_idle;