1caf44cfd039e7af7731264296b74a18fe644ab8
[openwrt/staging/stintel.git] /
1 From c53200aa7d0670aa21639512880669b94699aaee Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Tue, 15 Dec 2020 16:42:35 +0100
4 Subject: [PATCH] drm/vc4: hvs: Align the HVS atomic hooks to the new
5 API
6
7 Since the CRTC setup in vc4 is split between the PixelValves/TXP and the
8 HVS, only the PV/TXP atomic hooks were updated in the previous commits, but
9 it makes sense to update the HVS ones too.
10
11 Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
12 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
13 Link: https://patchwork.freedesktop.org/patch/msgid/20201215154243.540115-2-maxime@cerno.tech
14 ---
15 drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
16 drivers/gpu/drm/vc4/vc4_drv.h | 5 ++---
17 drivers/gpu/drm/vc4/vc4_hvs.c | 10 +++++-----
18 drivers/gpu/drm/vc4/vc4_txp.c | 2 +-
19 4 files changed, 9 insertions(+), 10 deletions(-)
20
21 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
22 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
23 @@ -646,7 +646,7 @@ static int vc4_crtc_atomic_check(struct
24 struct drm_connector_state *conn_state;
25 int ret, i;
26
27 - ret = vc4_hvs_atomic_check(crtc, crtc_state);
28 + ret = vc4_hvs_atomic_check(crtc, state);
29 if (ret)
30 return ret;
31
32 --- a/drivers/gpu/drm/vc4/vc4_drv.h
33 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
34 @@ -924,11 +924,10 @@ void vc4_irq_reset(struct drm_device *de
35 extern struct platform_driver vc4_hvs_driver;
36 void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
37 int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
38 -int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
39 +int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
40 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
41 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);
42 -void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
43 - struct drm_atomic_state *state);
44 +void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);
45 void vc4_hvs_dump_state(struct drm_device *dev);
46 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
47 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
48 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
49 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
50 @@ -365,10 +365,10 @@ void vc4_hvs_stop_channel(struct drm_dev
51 SCALER_DISPSTATX_EMPTY);
52 }
53
54 -int vc4_hvs_atomic_check(struct drm_crtc *crtc,
55 - struct drm_crtc_state *state)
56 +int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
57 {
58 - struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
59 + struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
60 + struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
61 struct drm_device *dev = crtc->dev;
62 struct vc4_dev *vc4 = to_vc4_dev(dev);
63 struct drm_plane *plane;
64 @@ -380,10 +380,10 @@ int vc4_hvs_atomic_check(struct drm_crtc
65 /* The pixelvalve can only feed one encoder (and encoders are
66 * 1:1 with connectors.)
67 */
68 - if (hweight32(state->connector_mask) > 1)
69 + if (hweight32(crtc_state->connector_mask) > 1)
70 return -EINVAL;
71
72 - drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
73 + drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state)
74 dlist_count += vc4_plane_dlist_size(plane_state);
75
76 dlist_count++; /* Account for SCALER_CTL0_END. */
77 --- a/drivers/gpu/drm/vc4/vc4_txp.c
78 +++ b/drivers/gpu/drm/vc4/vc4_txp.c
79 @@ -393,7 +393,7 @@ static int vc4_txp_atomic_check(struct d
80 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
81 int ret;
82
83 - ret = vc4_hvs_atomic_check(crtc, crtc_state);
84 + ret = vc4_hvs_atomic_check(crtc, state);
85 if (ret)
86 return ret;
87