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1 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
2 Date: Wed, 22 Sep 2021 07:00:34 +0200
3 Subject: [PATCH] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
4
5 Add driver for the PCIe controller of the MT7621 SoC.
6
7 [bhelgaas: rename from pci-mt7621.c to pcie-mt7621.c; also rename Kconfig
8 symbol from PCI_MT7621 to PCIE_MT7621]
9 Link: https://lore.kernel.org/r/20210922050035.18162-3-sergio.paracuellos@gmail.com
10 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
11 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
12 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
13 Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 ---
15 rename drivers/{staging/mt7621-pci/pci-mt7621.c => pci/controller/pcie-mt7621.c} (95%)
16 delete mode 100644 drivers/staging/mt7621-pci/Kconfig
17 delete mode 100644 drivers/staging/mt7621-pci/Makefile
18 delete mode 100644 drivers/staging/mt7621-pci/TODO
19 delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
20
21 --- a/arch/mips/ralink/Kconfig
22 +++ b/arch/mips/ralink/Kconfig
23 @@ -51,7 +51,8 @@ choice
24 select SYS_SUPPORTS_HIGHMEM
25 select MIPS_GIC
26 select CLKSRC_MIPS_GIC
27 - select HAVE_PCI if PCI_MT7621
28 + select HAVE_PCI
29 + select PCI_DRIVERS_GENERIC
30 select SOC_BUS
31 endchoice
32
33 --- a/drivers/pci/controller/Kconfig
34 +++ b/drivers/pci/controller/Kconfig
35 @@ -312,6 +312,14 @@ config PCIE_HISI_ERR
36 Say Y here if you want error handling support
37 for the PCIe controller's errors on HiSilicon HIP SoCs
38
39 +config PCIE_MT7621
40 + tristate "MediaTek MT7621 PCIe Controller"
41 + depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
42 + select PHY_MT7621_PCI
43 + default SOC_MT7621
44 + help
45 + This selects a driver for the MediaTek MT7621 PCIe Controller.
46 +
47 source "drivers/pci/controller/dwc/Kconfig"
48 source "drivers/pci/controller/mobiveil/Kconfig"
49 source "drivers/pci/controller/cadence/Kconfig"
50 --- a/drivers/pci/controller/Makefile
51 +++ b/drivers/pci/controller/Makefile
52 @@ -37,6 +37,8 @@ obj-$(CONFIG_VMD) += vmd.o
53 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
54 obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
55 obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
56 +obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
57 +
58 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
59 obj-y += dwc/
60 obj-y += mobiveil/
61 --- a/drivers/staging/Kconfig
62 +++ b/drivers/staging/Kconfig
63 @@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kc
64
65 source "drivers/staging/pi433/Kconfig"
66
67 -source "drivers/staging/mt7621-pci/Kconfig"
68 -
69 source "drivers/staging/mt7621-dma/Kconfig"
70
71 source "drivers/staging/ralink-gdma/Kconfig"
72 --- a/drivers/staging/Makefile
73 +++ b/drivers/staging/Makefile
74 @@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010) += ks7010/
75 obj-$(CONFIG_GREYBUS) += greybus/
76 obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/
77 obj-$(CONFIG_PI433) += pi433/
78 -obj-$(CONFIG_PCI_MT7621) += mt7621-pci/
79 obj-$(CONFIG_SOC_MT7621) += mt7621-dma/
80 obj-$(CONFIG_DMA_RALINK) += ralink-gdma/
81 obj-$(CONFIG_SOC_MT7621) += mt7621-dts/
82 --- a/drivers/staging/mt7621-pci/Kconfig
83 +++ /dev/null
84 @@ -1,8 +0,0 @@
85 -# SPDX-License-Identifier: GPL-2.0
86 -config PCI_MT7621
87 - tristate "MediaTek MT7621 PCI Controller"
88 - depends on RALINK
89 - select PCI_DRIVERS_GENERIC
90 - help
91 - This selects a driver for the MediaTek MT7621 PCI Controller.
92 -
93 --- a/drivers/staging/mt7621-pci/Makefile
94 +++ /dev/null
95 @@ -1,2 +0,0 @@
96 -# SPDX-License-Identifier: GPL-2.0
97 -obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o
98 --- a/drivers/staging/mt7621-pci/TODO
99 +++ /dev/null
100 @@ -1,4 +0,0 @@
101 -
102 -- general code review and cleanup
103 -
104 -Cc: NeilBrown <neil@brown.name>
105 --- a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
106 +++ /dev/null
107 @@ -1,104 +0,0 @@
108 -MediaTek MT7621 PCIe controller
109 -
110 -Required properties:
111 -- compatible: "mediatek,mt7621-pci"
112 -- device_type: Must be "pci"
113 -- reg: Base addresses and lengths of the PCIe subsys and root ports.
114 -- bus-range: Range of bus numbers associated with this controller.
115 -- #address-cells: Address representation for root ports (must be 3)
116 -- pinctrl-names : The pin control state names.
117 -- pinctrl-0: The "default" pinctrl state.
118 -- #size-cells: Size representation for root ports (must be 2)
119 -- ranges: Ranges for the PCI memory and I/O regions.
120 -- #interrupt-cells: Must be 1
121 -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
122 - Please refer to the standard PCI bus binding document for a more detailed
123 - explanation.
124 -- status: either "disabled" or "okay".
125 -- resets: Must contain an entry for each entry in reset-names.
126 - See ../reset/reset.txt for details.
127 -- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
128 - root ports.
129 -- clocks: Must contain an entry for each entry in clock-names.
130 - See ../clocks/clock-bindings.txt for details.
131 -- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
132 - root ports.
133 -- reset-gpios: GPIO specs for the reset pins.
134 -
135 -In addition, the device tree node must have sub-nodes describing each PCIe port
136 -interface, having the following mandatory properties:
137 -
138 -Required properties:
139 -- reg: Only the first four bytes are used to refer to the correct bus number
140 - and device number.
141 -- #address-cells: Must be 3
142 -- #size-cells: Must be 2
143 -- ranges: Sub-ranges distributed from the PCIe controller node. An empty
144 - property is sufficient.
145 -- bus-range: Range of bus numbers associated with this port.
146 -
147 -Example for MT7621:
148 -
149 - pcie: pcie@1e140000 {
150 - compatible = "mediatek,mt7621-pci";
151 - reg = <0x1e140000 0x100 /* host-pci bridge registers */
152 - 0x1e142000 0x100 /* pcie port 0 RC control registers */
153 - 0x1e143000 0x100 /* pcie port 1 RC control registers */
154 - 0x1e144000 0x100>; /* pcie port 2 RC control registers */
155 -
156 - #address-cells = <3>;
157 - #size-cells = <2>;
158 -
159 - pinctrl-names = "default";
160 - pinctrl-0 = <&pcie_pins>;
161 -
162 - device_type = "pci";
163 -
164 - bus-range = <0 255>;
165 - ranges = <
166 - 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
167 - 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
168 - >;
169 -
170 - #interrupt-cells = <1>;
171 - interrupt-map-mask = <0xF0000 0 0 1>;
172 - interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
173 - <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
174 - <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
175 -
176 - status = "disabled";
177 -
178 - resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
179 - reset-names = "pcie0", "pcie1", "pcie2";
180 - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
181 - clock-names = "pcie0", "pcie1", "pcie2";
182 -
183 - reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
184 - <&gpio 8 GPIO_ACTIVE_LOW>,
185 - <&gpio 7 GPIO_ACTIVE_LOW>;
186 -
187 - pcie@0,0 {
188 - reg = <0x0000 0 0 0 0>;
189 - #address-cells = <3>;
190 - #size-cells = <2>;
191 - ranges;
192 - bus-range = <0x00 0xff>;
193 - };
194 -
195 - pcie@1,0 {
196 - reg = <0x0800 0 0 0 0>;
197 - #address-cells = <3>;
198 - #size-cells = <2>;
199 - ranges;
200 - bus-range = <0x00 0xff>;
201 - };
202 -
203 - pcie@2,0 {
204 - reg = <0x1000 0 0 0 0>;
205 - #address-cells = <3>;
206 - #size-cells = <2>;
207 - ranges;
208 - bus-range = <0x00 0xff>;
209 - };
210 - };
211 -
212 --- a/drivers/staging/mt7621-pci/pci-mt7621.c
213 +++ /dev/null
214 @@ -1,601 +0,0 @@
215 -// SPDX-License-Identifier: GPL-2.0+
216 -/*
217 - * BRIEF MODULE DESCRIPTION
218 - * PCI init for Ralink RT2880 solution
219 - *
220 - * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
221 - *
222 - * May 2007 Bruce Chang
223 - * Initial Release
224 - *
225 - * May 2009 Bruce Chang
226 - * support RT2880/RT3883 PCIe
227 - *
228 - * May 2011 Bruce Chang
229 - * support RT6855/MT7620 PCIe
230 - */
231 -
232 -#include <linux/bitops.h>
233 -#include <linux/clk.h>
234 -#include <linux/delay.h>
235 -#include <linux/gpio/consumer.h>
236 -#include <linux/module.h>
237 -#include <linux/of.h>
238 -#include <linux/of_address.h>
239 -#include <linux/of_pci.h>
240 -#include <linux/of_platform.h>
241 -#include <linux/pci.h>
242 -#include <linux/phy/phy.h>
243 -#include <linux/platform_device.h>
244 -#include <linux/reset.h>
245 -#include <linux/sys_soc.h>
246 -
247 -/* MediaTek specific configuration registers */
248 -#define PCIE_FTS_NUM 0x70c
249 -#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
250 -#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
251 -
252 -/* Host-PCI bridge registers */
253 -#define RALINK_PCI_PCICFG_ADDR 0x0000
254 -#define RALINK_PCI_PCIMSK_ADDR 0x000C
255 -#define RALINK_PCI_CONFIG_ADDR 0x0020
256 -#define RALINK_PCI_CONFIG_DATA 0x0024
257 -#define RALINK_PCI_MEMBASE 0x0028
258 -#define RALINK_PCI_IOBASE 0x002C
259 -
260 -/* PCIe RC control registers */
261 -#define RALINK_PCI_ID 0x0030
262 -#define RALINK_PCI_CLASS 0x0034
263 -#define RALINK_PCI_SUBID 0x0038
264 -#define RALINK_PCI_STATUS 0x0050
265 -
266 -/* Some definition values */
267 -#define PCIE_REVISION_ID BIT(0)
268 -#define PCIE_CLASS_CODE (0x60400 << 8)
269 -#define PCIE_BAR_MAP_MAX GENMASK(30, 16)
270 -#define PCIE_BAR_ENABLE BIT(0)
271 -#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
272 -#define PCIE_PORT_LINKUP BIT(0)
273 -#define PCIE_PORT_CNT 3
274 -
275 -#define PERST_DELAY_MS 100
276 -
277 -/**
278 - * struct mt7621_pcie_port - PCIe port information
279 - * @base: I/O mapped register base
280 - * @list: port list
281 - * @pcie: pointer to PCIe host info
282 - * @clk: pointer to the port clock gate
283 - * @phy: pointer to PHY control block
284 - * @pcie_rst: pointer to port reset control
285 - * @gpio_rst: gpio reset
286 - * @slot: port slot
287 - * @enabled: indicates if port is enabled
288 - */
289 -struct mt7621_pcie_port {
290 - void __iomem *base;
291 - struct list_head list;
292 - struct mt7621_pcie *pcie;
293 - struct clk *clk;
294 - struct phy *phy;
295 - struct reset_control *pcie_rst;
296 - struct gpio_desc *gpio_rst;
297 - u32 slot;
298 - bool enabled;
299 -};
300 -
301 -/**
302 - * struct mt7621_pcie - PCIe host information
303 - * @base: IO Mapped Register Base
304 - * @dev: Pointer to PCIe device
305 - * @ports: pointer to PCIe port information
306 - * @resets_inverted: depends on chip revision
307 - * reset lines are inverted.
308 - */
309 -struct mt7621_pcie {
310 - struct device *dev;
311 - void __iomem *base;
312 - struct list_head ports;
313 - bool resets_inverted;
314 -};
315 -
316 -static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
317 -{
318 - return readl_relaxed(pcie->base + reg);
319 -}
320 -
321 -static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
322 -{
323 - writel_relaxed(val, pcie->base + reg);
324 -}
325 -
326 -static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
327 -{
328 - u32 val = readl_relaxed(pcie->base + reg);
329 -
330 - val &= ~clr;
331 - val |= set;
332 - writel_relaxed(val, pcie->base + reg);
333 -}
334 -
335 -static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
336 -{
337 - return readl_relaxed(port->base + reg);
338 -}
339 -
340 -static inline void pcie_port_write(struct mt7621_pcie_port *port,
341 - u32 val, u32 reg)
342 -{
343 - writel_relaxed(val, port->base + reg);
344 -}
345 -
346 -static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot,
347 - unsigned int func, unsigned int where)
348 -{
349 - return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
350 - (func << 8) | (where & 0xfc) | 0x80000000;
351 -}
352 -
353 -static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
354 - unsigned int devfn, int where)
355 -{
356 - struct mt7621_pcie *pcie = bus->sysdata;
357 - u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn),
358 - PCI_FUNC(devfn), where);
359 -
360 - writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
361 -
362 - return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
363 -}
364 -
365 -struct pci_ops mt7621_pcie_ops = {
366 - .map_bus = mt7621_pcie_map_bus,
367 - .read = pci_generic_config_read,
368 - .write = pci_generic_config_write,
369 -};
370 -
371 -static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
372 -{
373 - u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
374 -
375 - pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
376 - return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
377 -}
378 -
379 -static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
380 - u32 reg, u32 val)
381 -{
382 - u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
383 -
384 - pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
385 - pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
386 -}
387 -
388 -static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
389 -{
390 - if (port->gpio_rst)
391 - gpiod_set_value(port->gpio_rst, 1);
392 -}
393 -
394 -static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
395 -{
396 - if (port->gpio_rst)
397 - gpiod_set_value(port->gpio_rst, 0);
398 -}
399 -
400 -static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
401 -{
402 - return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
403 -}
404 -
405 -static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
406 -{
407 - struct mt7621_pcie *pcie = port->pcie;
408 -
409 - if (pcie->resets_inverted)
410 - reset_control_assert(port->pcie_rst);
411 - else
412 - reset_control_deassert(port->pcie_rst);
413 -}
414 -
415 -static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
416 -{
417 - struct mt7621_pcie *pcie = port->pcie;
418 -
419 - if (pcie->resets_inverted)
420 - reset_control_deassert(port->pcie_rst);
421 - else
422 - reset_control_assert(port->pcie_rst);
423 -}
424 -
425 -static int setup_cm_memory_region(struct pci_host_bridge *host)
426 -{
427 - struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
428 - struct device *dev = pcie->dev;
429 - struct resource_entry *entry;
430 - resource_size_t mask;
431 -
432 - entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
433 - if (!entry) {
434 - dev_err(dev, "Cannot get memory resource\n");
435 - return -EINVAL;
436 - }
437 -
438 - if (mips_cps_numiocu(0)) {
439 - /*
440 - * FIXME: hardware doesn't accept mask values with 1s after
441 - * 0s (e.g. 0xffef), so it would be great to warn if that's
442 - * about to happen
443 - */
444 - mask = ~(entry->res->end - entry->res->start);
445 -
446 - write_gcr_reg1_base(entry->res->start);
447 - write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
448 - dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
449 - (unsigned long long)read_gcr_reg1_base(),
450 - (unsigned long long)read_gcr_reg1_mask());
451 - }
452 -
453 - return 0;
454 -}
455 -
456 -static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
457 - struct device_node *node,
458 - int slot)
459 -{
460 - struct mt7621_pcie_port *port;
461 - struct device *dev = pcie->dev;
462 - struct platform_device *pdev = to_platform_device(dev);
463 - char name[10];
464 - int err;
465 -
466 - port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
467 - if (!port)
468 - return -ENOMEM;
469 -
470 - port->base = devm_platform_ioremap_resource(pdev, slot + 1);
471 - if (IS_ERR(port->base))
472 - return PTR_ERR(port->base);
473 -
474 - port->clk = devm_get_clk_from_child(dev, node, NULL);
475 - if (IS_ERR(port->clk)) {
476 - dev_err(dev, "failed to get pcie%d clock\n", slot);
477 - return PTR_ERR(port->clk);
478 - }
479 -
480 - port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
481 - if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
482 - dev_err(dev, "failed to get pcie%d reset control\n", slot);
483 - return PTR_ERR(port->pcie_rst);
484 - }
485 -
486 - snprintf(name, sizeof(name), "pcie-phy%d", slot);
487 - port->phy = devm_of_phy_get(dev, node, name);
488 - if (IS_ERR(port->phy)) {
489 - dev_err(dev, "failed to get pcie-phy%d\n", slot);
490 - err = PTR_ERR(port->phy);
491 - goto remove_reset;
492 - }
493 -
494 - port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
495 - GPIOD_OUT_LOW);
496 - if (IS_ERR(port->gpio_rst)) {
497 - dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
498 - err = PTR_ERR(port->gpio_rst);
499 - goto remove_reset;
500 - }
501 -
502 - port->slot = slot;
503 - port->pcie = pcie;
504 -
505 - INIT_LIST_HEAD(&port->list);
506 - list_add_tail(&port->list, &pcie->ports);
507 -
508 - return 0;
509 -
510 -remove_reset:
511 - reset_control_put(port->pcie_rst);
512 - return err;
513 -}
514 -
515 -static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
516 -{
517 - struct device *dev = pcie->dev;
518 - struct platform_device *pdev = to_platform_device(dev);
519 - struct device_node *node = dev->of_node, *child;
520 - int err;
521 -
522 - pcie->base = devm_platform_ioremap_resource(pdev, 0);
523 - if (IS_ERR(pcie->base))
524 - return PTR_ERR(pcie->base);
525 -
526 - for_each_available_child_of_node(node, child) {
527 - int slot;
528 -
529 - err = of_pci_get_devfn(child);
530 - if (err < 0) {
531 - of_node_put(child);
532 - dev_err(dev, "failed to parse devfn: %d\n", err);
533 - return err;
534 - }
535 -
536 - slot = PCI_SLOT(err);
537 -
538 - err = mt7621_pcie_parse_port(pcie, child, slot);
539 - if (err) {
540 - of_node_put(child);
541 - return err;
542 - }
543 - }
544 -
545 - return 0;
546 -}
547 -
548 -static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
549 -{
550 - struct mt7621_pcie *pcie = port->pcie;
551 - struct device *dev = pcie->dev;
552 - u32 slot = port->slot;
553 - int err;
554 -
555 - err = phy_init(port->phy);
556 - if (err) {
557 - dev_err(dev, "failed to initialize port%d phy\n", slot);
558 - return err;
559 - }
560 -
561 - err = phy_power_on(port->phy);
562 - if (err) {
563 - dev_err(dev, "failed to power on port%d phy\n", slot);
564 - phy_exit(port->phy);
565 - return err;
566 - }
567 -
568 - port->enabled = true;
569 -
570 - return 0;
571 -}
572 -
573 -static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
574 -{
575 - struct mt7621_pcie_port *port;
576 -
577 - list_for_each_entry(port, &pcie->ports, list) {
578 - /* PCIe RC reset assert */
579 - mt7621_control_assert(port);
580 -
581 - /* PCIe EP reset assert */
582 - mt7621_rst_gpio_pcie_assert(port);
583 - }
584 -
585 - msleep(PERST_DELAY_MS);
586 -}
587 -
588 -static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
589 -{
590 - struct mt7621_pcie_port *port;
591 -
592 - list_for_each_entry(port, &pcie->ports, list)
593 - mt7621_control_deassert(port);
594 -}
595 -
596 -static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
597 -{
598 - struct mt7621_pcie_port *port;
599 -
600 - list_for_each_entry(port, &pcie->ports, list)
601 - mt7621_rst_gpio_pcie_deassert(port);
602 -
603 - msleep(PERST_DELAY_MS);
604 -}
605 -
606 -static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
607 -{
608 - struct device *dev = pcie->dev;
609 - struct mt7621_pcie_port *port, *tmp;
610 - u8 num_disabled = 0;
611 - int err;
612 -
613 - mt7621_pcie_reset_assert(pcie);
614 - mt7621_pcie_reset_rc_deassert(pcie);
615 -
616 - list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
617 - u32 slot = port->slot;
618 -
619 - if (slot == 1) {
620 - port->enabled = true;
621 - continue;
622 - }
623 -
624 - err = mt7621_pcie_init_port(port);
625 - if (err) {
626 - dev_err(dev, "Initiating port %d failed\n", slot);
627 - list_del(&port->list);
628 - }
629 - }
630 -
631 - mt7621_pcie_reset_ep_deassert(pcie);
632 -
633 - tmp = NULL;
634 - list_for_each_entry(port, &pcie->ports, list) {
635 - u32 slot = port->slot;
636 -
637 - if (!mt7621_pcie_port_is_linkup(port)) {
638 - dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
639 - slot);
640 - mt7621_control_assert(port);
641 - port->enabled = false;
642 - num_disabled++;
643 -
644 - if (slot == 0) {
645 - tmp = port;
646 - continue;
647 - }
648 -
649 - if (slot == 1 && tmp && !tmp->enabled)
650 - phy_power_off(tmp->phy);
651 - }
652 - }
653 -
654 - return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
655 -}
656 -
657 -static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
658 -{
659 - struct mt7621_pcie *pcie = port->pcie;
660 - u32 slot = port->slot;
661 - u32 val;
662 -
663 - /* enable pcie interrupt */
664 - val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
665 - val |= PCIE_PORT_INT_EN(slot);
666 - pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
667 -
668 - /* map 2G DDR region */
669 - pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
670 - PCI_BASE_ADDRESS_0);
671 -
672 - /* configure class code and revision ID */
673 - pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
674 - RALINK_PCI_CLASS);
675 -
676 - /* configure RC FTS number to 250 when it leaves L0s */
677 - val = read_config(pcie, slot, PCIE_FTS_NUM);
678 - val &= ~PCIE_FTS_NUM_MASK;
679 - val |= PCIE_FTS_NUM_L0(0x50);
680 - write_config(pcie, slot, PCIE_FTS_NUM, val);
681 -}
682 -
683 -static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
684 -{
685 - struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
686 - struct device *dev = pcie->dev;
687 - struct mt7621_pcie_port *port;
688 - struct resource_entry *entry;
689 - int err;
690 -
691 - entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
692 - if (!entry) {
693 - dev_err(dev, "Cannot get io resource\n");
694 - return -EINVAL;
695 - }
696 -
697 - /* Setup MEMWIN and IOWIN */
698 - pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
699 - pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE);
700 -
701 - list_for_each_entry(port, &pcie->ports, list) {
702 - if (port->enabled) {
703 - err = clk_prepare_enable(port->clk);
704 - if (err) {
705 - dev_err(dev, "enabling clk pcie%d\n",
706 - port->slot);
707 - return err;
708 - }
709 -
710 - mt7621_pcie_enable_port(port);
711 - dev_info(dev, "PCIE%d enabled\n", port->slot);
712 - }
713 - }
714 -
715 - return 0;
716 -}
717 -
718 -static int mt7621_pcie_register_host(struct pci_host_bridge *host)
719 -{
720 - struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
721 -
722 - host->ops = &mt7621_pcie_ops;
723 - host->sysdata = pcie;
724 - return pci_host_probe(host);
725 -}
726 -
727 -static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
728 - { .soc_id = "mt7621", .revision = "E2" },
729 - { /* sentinel */ }
730 -};
731 -
732 -static int mt7621_pcie_probe(struct platform_device *pdev)
733 -{
734 - struct device *dev = &pdev->dev;
735 - const struct soc_device_attribute *attr;
736 - struct mt7621_pcie_port *port;
737 - struct mt7621_pcie *pcie;
738 - struct pci_host_bridge *bridge;
739 - int err;
740 -
741 - if (!dev->of_node)
742 - return -ENODEV;
743 -
744 - bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
745 - if (!bridge)
746 - return -ENOMEM;
747 -
748 - pcie = pci_host_bridge_priv(bridge);
749 - pcie->dev = dev;
750 - platform_set_drvdata(pdev, pcie);
751 - INIT_LIST_HEAD(&pcie->ports);
752 -
753 - attr = soc_device_match(mt7621_pcie_quirks_match);
754 - if (attr)
755 - pcie->resets_inverted = true;
756 -
757 - err = mt7621_pcie_parse_dt(pcie);
758 - if (err) {
759 - dev_err(dev, "Parsing DT failed\n");
760 - return err;
761 - }
762 -
763 - err = mt7621_pcie_init_ports(pcie);
764 - if (err) {
765 - dev_err(dev, "Nothing connected in virtual bridges\n");
766 - return 0;
767 - }
768 -
769 - err = mt7621_pcie_enable_ports(bridge);
770 - if (err) {
771 - dev_err(dev, "Error enabling pcie ports\n");
772 - goto remove_resets;
773 - }
774 -
775 - err = setup_cm_memory_region(bridge);
776 - if (err) {
777 - dev_err(dev, "Error setting up iocu mem regions\n");
778 - goto remove_resets;
779 - }
780 -
781 - return mt7621_pcie_register_host(bridge);
782 -
783 -remove_resets:
784 - list_for_each_entry(port, &pcie->ports, list)
785 - reset_control_put(port->pcie_rst);
786 -
787 - return err;
788 -}
789 -
790 -static int mt7621_pcie_remove(struct platform_device *pdev)
791 -{
792 - struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
793 - struct mt7621_pcie_port *port;
794 -
795 - list_for_each_entry(port, &pcie->ports, list)
796 - reset_control_put(port->pcie_rst);
797 -
798 - return 0;
799 -}
800 -
801 -static const struct of_device_id mt7621_pcie_ids[] = {
802 - { .compatible = "mediatek,mt7621-pci" },
803 - {},
804 -};
805 -MODULE_DEVICE_TABLE(of, mt7621_pcie_ids);
806 -
807 -static struct platform_driver mt7621_pcie_driver = {
808 - .probe = mt7621_pcie_probe,
809 - .remove = mt7621_pcie_remove,
810 - .driver = {
811 - .name = "mt7621-pci",
812 - .of_match_table = of_match_ptr(mt7621_pcie_ids),
813 - },
814 -};
815 -builtin_platform_driver(mt7621_pcie_driver);
816 --- /dev/null
817 +++ b/drivers/pci/controller/pcie-mt7621.c
818 @@ -0,0 +1,600 @@
819 +// SPDX-License-Identifier: GPL-2.0+
820 +/*
821 + * BRIEF MODULE DESCRIPTION
822 + * PCI init for Ralink RT2880 solution
823 + *
824 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
825 + *
826 + * May 2007 Bruce Chang
827 + * Initial Release
828 + *
829 + * May 2009 Bruce Chang
830 + * support RT2880/RT3883 PCIe
831 + *
832 + * May 2011 Bruce Chang
833 + * support RT6855/MT7620 PCIe
834 + */
835 +
836 +#include <linux/bitops.h>
837 +#include <linux/clk.h>
838 +#include <linux/delay.h>
839 +#include <linux/gpio/consumer.h>
840 +#include <linux/module.h>
841 +#include <linux/of.h>
842 +#include <linux/of_address.h>
843 +#include <linux/of_pci.h>
844 +#include <linux/of_platform.h>
845 +#include <linux/pci.h>
846 +#include <linux/phy/phy.h>
847 +#include <linux/platform_device.h>
848 +#include <linux/reset.h>
849 +#include <linux/sys_soc.h>
850 +
851 +/* MediaTek-specific configuration registers */
852 +#define PCIE_FTS_NUM 0x70c
853 +#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
854 +#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
855 +
856 +/* Host-PCI bridge registers */
857 +#define RALINK_PCI_PCICFG_ADDR 0x0000
858 +#define RALINK_PCI_PCIMSK_ADDR 0x000c
859 +#define RALINK_PCI_CONFIG_ADDR 0x0020
860 +#define RALINK_PCI_CONFIG_DATA 0x0024
861 +#define RALINK_PCI_MEMBASE 0x0028
862 +#define RALINK_PCI_IOBASE 0x002c
863 +
864 +/* PCIe RC control registers */
865 +#define RALINK_PCI_ID 0x0030
866 +#define RALINK_PCI_CLASS 0x0034
867 +#define RALINK_PCI_SUBID 0x0038
868 +#define RALINK_PCI_STATUS 0x0050
869 +
870 +/* Some definition values */
871 +#define PCIE_REVISION_ID BIT(0)
872 +#define PCIE_CLASS_CODE (0x60400 << 8)
873 +#define PCIE_BAR_MAP_MAX GENMASK(30, 16)
874 +#define PCIE_BAR_ENABLE BIT(0)
875 +#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
876 +#define PCIE_PORT_LINKUP BIT(0)
877 +#define PCIE_PORT_CNT 3
878 +
879 +#define PERST_DELAY_MS 100
880 +
881 +/**
882 + * struct mt7621_pcie_port - PCIe port information
883 + * @base: I/O mapped register base
884 + * @list: port list
885 + * @pcie: pointer to PCIe host info
886 + * @clk: pointer to the port clock gate
887 + * @phy: pointer to PHY control block
888 + * @pcie_rst: pointer to port reset control
889 + * @gpio_rst: gpio reset
890 + * @slot: port slot
891 + * @enabled: indicates if port is enabled
892 + */
893 +struct mt7621_pcie_port {
894 + void __iomem *base;
895 + struct list_head list;
896 + struct mt7621_pcie *pcie;
897 + struct clk *clk;
898 + struct phy *phy;
899 + struct reset_control *pcie_rst;
900 + struct gpio_desc *gpio_rst;
901 + u32 slot;
902 + bool enabled;
903 +};
904 +
905 +/**
906 + * struct mt7621_pcie - PCIe host information
907 + * @base: IO Mapped Register Base
908 + * @dev: Pointer to PCIe device
909 + * @ports: pointer to PCIe port information
910 + * @resets_inverted: depends on chip revision
911 + * reset lines are inverted.
912 + */
913 +struct mt7621_pcie {
914 + void __iomem *base;
915 + struct device *dev;
916 + struct list_head ports;
917 + bool resets_inverted;
918 +};
919 +
920 +static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
921 +{
922 + return readl_relaxed(pcie->base + reg);
923 +}
924 +
925 +static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
926 +{
927 + writel_relaxed(val, pcie->base + reg);
928 +}
929 +
930 +static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
931 +{
932 + u32 val = readl_relaxed(pcie->base + reg);
933 +
934 + val &= ~clr;
935 + val |= set;
936 + writel_relaxed(val, pcie->base + reg);
937 +}
938 +
939 +static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
940 +{
941 + return readl_relaxed(port->base + reg);
942 +}
943 +
944 +static inline void pcie_port_write(struct mt7621_pcie_port *port,
945 + u32 val, u32 reg)
946 +{
947 + writel_relaxed(val, port->base + reg);
948 +}
949 +
950 +static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
951 + unsigned int func, unsigned int where)
952 +{
953 + return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
954 + (func << 8) | (where & 0xfc) | 0x80000000;
955 +}
956 +
957 +static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
958 + unsigned int devfn, int where)
959 +{
960 + struct mt7621_pcie *pcie = bus->sysdata;
961 + u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
962 + PCI_FUNC(devfn), where);
963 +
964 + writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
965 +
966 + return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
967 +}
968 +
969 +struct pci_ops mt7621_pci_ops = {
970 + .map_bus = mt7621_pcie_map_bus,
971 + .read = pci_generic_config_read,
972 + .write = pci_generic_config_write,
973 +};
974 +
975 +static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
976 +{
977 + u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
978 +
979 + pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
980 + return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
981 +}
982 +
983 +static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
984 + u32 reg, u32 val)
985 +{
986 + u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
987 +
988 + pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
989 + pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
990 +}
991 +
992 +static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
993 +{
994 + if (port->gpio_rst)
995 + gpiod_set_value(port->gpio_rst, 1);
996 +}
997 +
998 +static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
999 +{
1000 + if (port->gpio_rst)
1001 + gpiod_set_value(port->gpio_rst, 0);
1002 +}
1003 +
1004 +static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
1005 +{
1006 + return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
1007 +}
1008 +
1009 +static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
1010 +{
1011 + struct mt7621_pcie *pcie = port->pcie;
1012 +
1013 + if (pcie->resets_inverted)
1014 + reset_control_assert(port->pcie_rst);
1015 + else
1016 + reset_control_deassert(port->pcie_rst);
1017 +}
1018 +
1019 +static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
1020 +{
1021 + struct mt7621_pcie *pcie = port->pcie;
1022 +
1023 + if (pcie->resets_inverted)
1024 + reset_control_deassert(port->pcie_rst);
1025 + else
1026 + reset_control_assert(port->pcie_rst);
1027 +}
1028 +
1029 +static int setup_cm_memory_region(struct pci_host_bridge *host)
1030 +{
1031 + struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
1032 + struct device *dev = pcie->dev;
1033 + struct resource_entry *entry;
1034 + resource_size_t mask;
1035 +
1036 + entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
1037 + if (!entry) {
1038 + dev_err(dev, "cannot get memory resource\n");
1039 + return -EINVAL;
1040 + }
1041 +
1042 + if (mips_cps_numiocu(0)) {
1043 + /*
1044 + * FIXME: hardware doesn't accept mask values with 1s after
1045 + * 0s (e.g. 0xffef), so it would be great to warn if that's
1046 + * about to happen
1047 + */
1048 + mask = ~(entry->res->end - entry->res->start);
1049 +
1050 + write_gcr_reg1_base(entry->res->start);
1051 + write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
1052 + dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
1053 + (unsigned long long)read_gcr_reg1_base(),
1054 + (unsigned long long)read_gcr_reg1_mask());
1055 + }
1056 +
1057 + return 0;
1058 +}
1059 +
1060 +static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
1061 + struct device_node *node,
1062 + int slot)
1063 +{
1064 + struct mt7621_pcie_port *port;
1065 + struct device *dev = pcie->dev;
1066 + struct platform_device *pdev = to_platform_device(dev);
1067 + char name[10];
1068 + int err;
1069 +
1070 + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
1071 + if (!port)
1072 + return -ENOMEM;
1073 +
1074 + port->base = devm_platform_ioremap_resource(pdev, slot + 1);
1075 + if (IS_ERR(port->base))
1076 + return PTR_ERR(port->base);
1077 +
1078 + port->clk = devm_get_clk_from_child(dev, node, NULL);
1079 + if (IS_ERR(port->clk)) {
1080 + dev_err(dev, "failed to get pcie%d clock\n", slot);
1081 + return PTR_ERR(port->clk);
1082 + }
1083 +
1084 + port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
1085 + if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
1086 + dev_err(dev, "failed to get pcie%d reset control\n", slot);
1087 + return PTR_ERR(port->pcie_rst);
1088 + }
1089 +
1090 + snprintf(name, sizeof(name), "pcie-phy%d", slot);
1091 + port->phy = devm_of_phy_get(dev, node, name);
1092 + if (IS_ERR(port->phy)) {
1093 + dev_err(dev, "failed to get pcie-phy%d\n", slot);
1094 + err = PTR_ERR(port->phy);
1095 + goto remove_reset;
1096 + }
1097 +
1098 + port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
1099 + GPIOD_OUT_LOW);
1100 + if (IS_ERR(port->gpio_rst)) {
1101 + dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
1102 + err = PTR_ERR(port->gpio_rst);
1103 + goto remove_reset;
1104 + }
1105 +
1106 + port->slot = slot;
1107 + port->pcie = pcie;
1108 +
1109 + INIT_LIST_HEAD(&port->list);
1110 + list_add_tail(&port->list, &pcie->ports);
1111 +
1112 + return 0;
1113 +
1114 +remove_reset:
1115 + reset_control_put(port->pcie_rst);
1116 + return err;
1117 +}
1118 +
1119 +static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
1120 +{
1121 + struct device *dev = pcie->dev;
1122 + struct platform_device *pdev = to_platform_device(dev);
1123 + struct device_node *node = dev->of_node, *child;
1124 + int err;
1125 +
1126 + pcie->base = devm_platform_ioremap_resource(pdev, 0);
1127 + if (IS_ERR(pcie->base))
1128 + return PTR_ERR(pcie->base);
1129 +
1130 + for_each_available_child_of_node(node, child) {
1131 + int slot;
1132 +
1133 + err = of_pci_get_devfn(child);
1134 + if (err < 0) {
1135 + of_node_put(child);
1136 + dev_err(dev, "failed to parse devfn: %d\n", err);
1137 + return err;
1138 + }
1139 +
1140 + slot = PCI_SLOT(err);
1141 +
1142 + err = mt7621_pcie_parse_port(pcie, child, slot);
1143 + if (err) {
1144 + of_node_put(child);
1145 + return err;
1146 + }
1147 + }
1148 +
1149 + return 0;
1150 +}
1151 +
1152 +static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
1153 +{
1154 + struct mt7621_pcie *pcie = port->pcie;
1155 + struct device *dev = pcie->dev;
1156 + u32 slot = port->slot;
1157 + int err;
1158 +
1159 + err = phy_init(port->phy);
1160 + if (err) {
1161 + dev_err(dev, "failed to initialize port%d phy\n", slot);
1162 + return err;
1163 + }
1164 +
1165 + err = phy_power_on(port->phy);
1166 + if (err) {
1167 + dev_err(dev, "failed to power on port%d phy\n", slot);
1168 + phy_exit(port->phy);
1169 + return err;
1170 + }
1171 +
1172 + port->enabled = true;
1173 +
1174 + return 0;
1175 +}
1176 +
1177 +static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
1178 +{
1179 + struct mt7621_pcie_port *port;
1180 +
1181 + list_for_each_entry(port, &pcie->ports, list) {
1182 + /* PCIe RC reset assert */
1183 + mt7621_control_assert(port);
1184 +
1185 + /* PCIe EP reset assert */
1186 + mt7621_rst_gpio_pcie_assert(port);
1187 + }
1188 +
1189 + msleep(PERST_DELAY_MS);
1190 +}
1191 +
1192 +static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
1193 +{
1194 + struct mt7621_pcie_port *port;
1195 +
1196 + list_for_each_entry(port, &pcie->ports, list)
1197 + mt7621_control_deassert(port);
1198 +}
1199 +
1200 +static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
1201 +{
1202 + struct mt7621_pcie_port *port;
1203 +
1204 + list_for_each_entry(port, &pcie->ports, list)
1205 + mt7621_rst_gpio_pcie_deassert(port);
1206 +
1207 + msleep(PERST_DELAY_MS);
1208 +}
1209 +
1210 +static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
1211 +{
1212 + struct device *dev = pcie->dev;
1213 + struct mt7621_pcie_port *port, *tmp;
1214 + u8 num_disabled = 0;
1215 + int err;
1216 +
1217 + mt7621_pcie_reset_assert(pcie);
1218 + mt7621_pcie_reset_rc_deassert(pcie);
1219 +
1220 + list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1221 + u32 slot = port->slot;
1222 +
1223 + if (slot == 1) {
1224 + port->enabled = true;
1225 + continue;
1226 + }
1227 +
1228 + err = mt7621_pcie_init_port(port);
1229 + if (err) {
1230 + dev_err(dev, "initializing port %d failed\n", slot);
1231 + list_del(&port->list);
1232 + }
1233 + }
1234 +
1235 + mt7621_pcie_reset_ep_deassert(pcie);
1236 +
1237 + tmp = NULL;
1238 + list_for_each_entry(port, &pcie->ports, list) {
1239 + u32 slot = port->slot;
1240 +
1241 + if (!mt7621_pcie_port_is_linkup(port)) {
1242 + dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
1243 + slot);
1244 + mt7621_control_assert(port);
1245 + port->enabled = false;
1246 + num_disabled++;
1247 +
1248 + if (slot == 0) {
1249 + tmp = port;
1250 + continue;
1251 + }
1252 +
1253 + if (slot == 1 && tmp && !tmp->enabled)
1254 + phy_power_off(tmp->phy);
1255 + }
1256 + }
1257 +
1258 + return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
1259 +}
1260 +
1261 +static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
1262 +{
1263 + struct mt7621_pcie *pcie = port->pcie;
1264 + u32 slot = port->slot;
1265 + u32 val;
1266 +
1267 + /* enable pcie interrupt */
1268 + val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
1269 + val |= PCIE_PORT_INT_EN(slot);
1270 + pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
1271 +
1272 + /* map 2G DDR region */
1273 + pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
1274 + PCI_BASE_ADDRESS_0);
1275 +
1276 + /* configure class code and revision ID */
1277 + pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
1278 + RALINK_PCI_CLASS);
1279 +
1280 + /* configure RC FTS number to 250 when it leaves L0s */
1281 + val = read_config(pcie, slot, PCIE_FTS_NUM);
1282 + val &= ~PCIE_FTS_NUM_MASK;
1283 + val |= PCIE_FTS_NUM_L0(0x50);
1284 + write_config(pcie, slot, PCIE_FTS_NUM, val);
1285 +}
1286 +
1287 +static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
1288 +{
1289 + struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
1290 + struct device *dev = pcie->dev;
1291 + struct mt7621_pcie_port *port;
1292 + struct resource_entry *entry;
1293 + int err;
1294 +
1295 + entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
1296 + if (!entry) {
1297 + dev_err(dev, "cannot get io resource\n");
1298 + return -EINVAL;
1299 + }
1300 +
1301 + /* Setup MEMWIN and IOWIN */
1302 + pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
1303 + pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE);
1304 +
1305 + list_for_each_entry(port, &pcie->ports, list) {
1306 + if (port->enabled) {
1307 + err = clk_prepare_enable(port->clk);
1308 + if (err) {
1309 + dev_err(dev, "enabling clk pcie%d\n",
1310 + port->slot);
1311 + return err;
1312 + }
1313 +
1314 + mt7621_pcie_enable_port(port);
1315 + dev_info(dev, "PCIE%d enabled\n", port->slot);
1316 + }
1317 + }
1318 +
1319 + return 0;
1320 +}
1321 +
1322 +static int mt7621_pcie_register_host(struct pci_host_bridge *host)
1323 +{
1324 + struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
1325 +
1326 + host->ops = &mt7621_pci_ops;
1327 + host->sysdata = pcie;
1328 + return pci_host_probe(host);
1329 +}
1330 +
1331 +static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
1332 + { .soc_id = "mt7621", .revision = "E2" }
1333 +};
1334 +
1335 +static int mt7621_pci_probe(struct platform_device *pdev)
1336 +{
1337 + struct device *dev = &pdev->dev;
1338 + const struct soc_device_attribute *attr;
1339 + struct mt7621_pcie_port *port;
1340 + struct mt7621_pcie *pcie;
1341 + struct pci_host_bridge *bridge;
1342 + int err;
1343 +
1344 + if (!dev->of_node)
1345 + return -ENODEV;
1346 +
1347 + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1348 + if (!bridge)
1349 + return -ENOMEM;
1350 +
1351 + pcie = pci_host_bridge_priv(bridge);
1352 + pcie->dev = dev;
1353 + platform_set_drvdata(pdev, pcie);
1354 + INIT_LIST_HEAD(&pcie->ports);
1355 +
1356 + attr = soc_device_match(mt7621_pci_quirks_match);
1357 + if (attr)
1358 + pcie->resets_inverted = true;
1359 +
1360 + err = mt7621_pcie_parse_dt(pcie);
1361 + if (err) {
1362 + dev_err(dev, "parsing DT failed\n");
1363 + return err;
1364 + }
1365 +
1366 + err = mt7621_pcie_init_ports(pcie);
1367 + if (err) {
1368 + dev_err(dev, "nothing connected in virtual bridges\n");
1369 + return 0;
1370 + }
1371 +
1372 + err = mt7621_pcie_enable_ports(bridge);
1373 + if (err) {
1374 + dev_err(dev, "error enabling pcie ports\n");
1375 + goto remove_resets;
1376 + }
1377 +
1378 + err = setup_cm_memory_region(bridge);
1379 + if (err) {
1380 + dev_err(dev, "error setting up iocu mem regions\n");
1381 + goto remove_resets;
1382 + }
1383 +
1384 + return mt7621_pcie_register_host(bridge);
1385 +
1386 +remove_resets:
1387 + list_for_each_entry(port, &pcie->ports, list)
1388 + reset_control_put(port->pcie_rst);
1389 +
1390 + return err;
1391 +}
1392 +
1393 +static int mt7621_pci_remove(struct platform_device *pdev)
1394 +{
1395 + struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
1396 + struct mt7621_pcie_port *port;
1397 +
1398 + list_for_each_entry(port, &pcie->ports, list)
1399 + reset_control_put(port->pcie_rst);
1400 +
1401 + return 0;
1402 +}
1403 +
1404 +static const struct of_device_id mt7621_pci_ids[] = {
1405 + { .compatible = "mediatek,mt7621-pci" },
1406 + {},
1407 +};
1408 +MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
1409 +
1410 +static struct platform_driver mt7621_pci_driver = {
1411 + .probe = mt7621_pci_probe,
1412 + .remove = mt7621_pci_remove,
1413 + .driver = {
1414 + .name = "mt7621-pci",
1415 + .of_match_table = of_match_ptr(mt7621_pci_ids),
1416 + },
1417 +};
1418 +builtin_platform_driver(mt7621_pci_driver);
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