git.openwrt.org Git - openwrt/staging/rmilecki.git/blob

   1 From e95b5a576032897a028c445c08d534440ebd1065 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Fri, 28 Sep 2018 16:21:24 -0700
   4 Subject: [PATCH 560/782] drm/v3d: Add a little debugfs entry for measuring the
   5  core clock.
   6
   7 This adds just enough performance counter support to measure the
   8 clock.  We don't have linux kernel drivers for the clock driving the
   9 HW, and this was useful for determining that the V3D HW is running on
  10 a slow clock, not that the driver was slow.
  11
  12 Signed-off-by: Eric Anholt <eric@anholt.net>
  13 Link: https://patchwork.freedesktop.org/patch/msgid/20180928232126.4332-2-eric@anholt.net
  14 Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
  15 (cherry picked from commit 6915c9a525e575732429c22b28eb11871a29374b)
  16 ---
  17  drivers/gpu/drm/v3d/v3d_debugfs.c | 35 +++++++++++++++++++++++++++++++
  18  drivers/gpu/drm/v3d/v3d_regs.h    | 30 ++++++++++++++++++++++++++
  19  2 files changed, 65 insertions(+)
  20
  21 --- a/drivers/gpu/drm/v3d/v3d_debugfs.c
  22 +++ b/drivers/gpu/drm/v3d/v3d_debugfs.c
  23 @@ -179,9 +179,44 @@ static int v3d_debugfs_bo_stats(struct s
  24         return 0;
  25  }
  26
  27 +static int v3d_measure_clock(struct seq_file *m, void *unused)
  28 +{
  29 +       struct drm_info_node *node = (struct drm_info_node *)m->private;
  30 +       struct drm_device *dev = node->minor->dev;
  31 +       struct v3d_dev *v3d = to_v3d_dev(dev);
  32 +       uint32_t cycles;
  33 +       int core = 0;
  34 +       int measure_ms = 1000;
  35 +
  36 +       if (v3d->ver >= 40) {
  37 +               V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
  38 +                              V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
  39 +                                            V3D_PCTR_S0));
  40 +               V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
  41 +               V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
  42 +       } else {
  43 +               V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
  44 +                              V3D_PCTR_CYCLE_COUNT);
  45 +               V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
  46 +               V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
  47 +                              V3D_V3_PCTR_0_EN_ENABLE |
  48 +                              1);
  49 +       }
  50 +       msleep(measure_ms);
  51 +       cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
  52 +
  53 +       seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
  54 +                  cycles,
  55 +                  cycles / (measure_ms * 1000),
  56 +                  (cycles / (measure_ms * 100)) % 10);
  57 +
  58 +       return 0;
  59 +}
  60 +
  61  static const struct drm_info_list v3d_debugfs_list[] = {
  62         {"v3d_ident", v3d_v3d_debugfs_ident, 0},
  63         {"v3d_regs", v3d_v3d_debugfs_regs, 0},
  64 +       {"measure_clock", v3d_measure_clock, 0},
  65         {"bo_stats", v3d_debugfs_bo_stats, 0},
  66  };
  67
  68 --- a/drivers/gpu/drm/v3d/v3d_regs.h
  69 +++ b/drivers/gpu/drm/v3d/v3d_regs.h
  70 @@ -267,6 +267,36 @@
  71  # define V3D_PTB_BXCF_RWORDERDISA                      BIT(1)
  72  # define V3D_PTB_BXCF_CLIPDISA                         BIT(0)
  73
  74 +#define V3D_V3_PCTR_0_EN                               0x00674
  75 +#define V3D_V3_PCTR_0_EN_ENABLE                        BIT(31)
  76 +#define V3D_V4_PCTR_0_EN                               0x00650
  77 +/* When a bit is set, resets the counter to 0. */
  78 +#define V3D_V3_PCTR_0_CLR                              0x00670
  79 +#define V3D_V4_PCTR_0_CLR                              0x00654
  80 +#define V3D_PCTR_0_OVERFLOW                            0x00658
  81 +
  82 +#define V3D_V3_PCTR_0_PCTRS0                           0x00684
  83 +#define V3D_V3_PCTR_0_PCTRS15                          0x00660
  84 +#define V3D_V3_PCTR_0_PCTRSX(x)                        (V3D_V3_PCTR_0_PCTRS0 + \
  85 +                                                       4 * (x))
  86 +/* Each src reg muxes four counters each. */
  87 +#define V3D_V4_PCTR_0_SRC_0_3                          0x00660
  88 +#define V3D_V4_PCTR_0_SRC_28_31                        0x0067c
  89 +# define V3D_PCTR_S0_MASK                              V3D_MASK(6, 0)
  90 +# define V3D_PCTR_S0_SHIFT                             0
  91 +# define V3D_PCTR_S1_MASK                              V3D_MASK(14, 8)
  92 +# define V3D_PCTR_S1_SHIFT                             8
  93 +# define V3D_PCTR_S2_MASK                              V3D_MASK(22, 16)
  94 +# define V3D_PCTR_S2_SHIFT                             16
  95 +# define V3D_PCTR_S3_MASK                              V3D_MASK(30, 24)
  96 +# define V3D_PCTR_S3_SHIFT                             24
  97 +# define V3D_PCTR_CYCLE_COUNT                          32
  98 +
  99 +/* Output values of the counters. */
 100 +#define V3D_PCTR_0_PCTR0                               0x00680
 101 +#define V3D_PCTR_0_PCTR31                              0x006fc
 102 +#define V3D_PCTR_0_PCTRX(x)                            (V3D_PCTR_0_PCTR0 + \
 103 +                                                       4 * (x))
 104  #define V3D_GMP_STATUS                                 0x00800
 105  # define V3D_GMP_STATUS_GMPRST                         BIT(31)
 106  # define V3D_GMP_STATUS_WR_COUNT_MASK                  V3D_MASK(30, 24)