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1 From a28533c6be1711584bf3ec978309d5c590029821 Mon Sep 17 00:00:00 2001
2 From: Shiji Yang <yangshiji66@outlook.com>
3 Date: Thu, 19 Oct 2023 19:58:57 +0800
4 Subject: wifi: rt2x00: rework MT7620 channel config function
5
6 1. Move the channel configuration code from rt2800_vco_calibration()
7 to the rt2800_config_channel().
8 2. Use MT7620 SoC specific AGC initial LNA value instead of the
9 RT5592's value.
10 3. BBP{195,196} pairing write has been replaced with
11 rt2800_bbp_glrt_write() to reduce redundant code.
12
13 Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
14 Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
15 Signed-off-by: Kalle Valo <kvalo@kernel.org>
16 Link: https://lore.kernel.org/r/TYAP286MB0315622A4340BFFA530B1B86BCD4A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
17 ---
18 drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 91 ++++++++++----------------
19 1 file changed, 35 insertions(+), 56 deletions(-)
20
21 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
22 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
23 @@ -3861,14 +3861,6 @@ static void rt2800_config_channel_rf7620
24 rfcsr |= tx_agc_fc;
25 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
26 }
27 -
28 - if (conf_is_ht40(conf)) {
29 - rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
30 - rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
31 - } else {
32 - rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
33 - rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
34 - }
35 }
36
37 static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
38 @@ -4437,32 +4429,46 @@ static void rt2800_config_channel(struct
39 usleep_range(1000, 1500);
40 }
41
42 - if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
43 - reg = 0x10;
44 - if (!conf_is_ht40(conf)) {
45 - if (rt2x00_rt(rt2x00dev, RT6352) &&
46 - rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
47 - reg |= 0x5;
48 - } else {
49 - reg |= 0xa;
50 - }
51 - }
52 - rt2800_bbp_write(rt2x00dev, 195, 141);
53 - rt2800_bbp_write(rt2x00dev, 196, reg);
54 + if (rt2x00_rt(rt2x00dev, RT5592)) {
55 + bbp = conf_is_ht40(conf) ? 0x10 : 0x1a;
56 + rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
57
58 - /* AGC init.
59 - * Despite the vendor driver using different values here for
60 - * RT6352 chip, we use 0x1c for now. This may have to be changed
61 - * once TSSI got implemented.
62 - */
63 - reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
64 - rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
65 + bbp = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
66 + rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
67
68 - if (rt2x00_rt(rt2x00dev, RT5592))
69 - rt2800_iq_calibrate(rt2x00dev, rf->channel);
70 + rt2800_iq_calibrate(rt2x00dev, rf->channel);
71 }
72
73 if (rt2x00_rt(rt2x00dev, RT6352)) {
74 + /* BBP for GLRT BW */
75 + bbp = conf_is_ht40(conf) ?
76 + 0x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ?
77 + 0x15 : 0x1a;
78 + rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
79 +
80 + bbp = conf_is_ht40(conf) ? 0x2f : 0x40;
81 + rt2800_bbp_glrt_write(rt2x00dev, 157, bbp);
82 +
83 + if (rt2x00dev->default_ant.rx_chain_num == 1) {
84 + rt2800_bbp_write(rt2x00dev, 91, 0x07);
85 + rt2800_bbp_write(rt2x00dev, 95, 0x1a);
86 + rt2800_bbp_glrt_write(rt2x00dev, 128, 0xa0);
87 + rt2800_bbp_glrt_write(rt2x00dev, 170, 0x12);
88 + rt2800_bbp_glrt_write(rt2x00dev, 171, 0x10);
89 + } else {
90 + rt2800_bbp_write(rt2x00dev, 91, 0x06);
91 + rt2800_bbp_write(rt2x00dev, 95, 0x9a);
92 + rt2800_bbp_glrt_write(rt2x00dev, 128, 0xe0);
93 + rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
94 + rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
95 + }
96 +
97 + /* AGC init */
98 + bbp = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0;
99 + rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
100 +
101 + usleep_range(1000, 1500);
102 +
103 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
104 &rt2x00dev->cap_flags)) {
105 reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
106 @@ -5608,26 +5614,6 @@ void rt2800_vco_calibration(struct rt2x0
107 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
108
109 if (rt2x00_rt(rt2x00dev, RT6352)) {
110 - if (rt2x00dev->default_ant.rx_chain_num == 1) {
111 - rt2800_bbp_write(rt2x00dev, 91, 0x07);
112 - rt2800_bbp_write(rt2x00dev, 95, 0x1A);
113 - rt2800_bbp_write(rt2x00dev, 195, 128);
114 - rt2800_bbp_write(rt2x00dev, 196, 0xA0);
115 - rt2800_bbp_write(rt2x00dev, 195, 170);
116 - rt2800_bbp_write(rt2x00dev, 196, 0x12);
117 - rt2800_bbp_write(rt2x00dev, 195, 171);
118 - rt2800_bbp_write(rt2x00dev, 196, 0x10);
119 - } else {
120 - rt2800_bbp_write(rt2x00dev, 91, 0x06);
121 - rt2800_bbp_write(rt2x00dev, 95, 0x9A);
122 - rt2800_bbp_write(rt2x00dev, 195, 128);
123 - rt2800_bbp_write(rt2x00dev, 196, 0xE0);
124 - rt2800_bbp_write(rt2x00dev, 195, 170);
125 - rt2800_bbp_write(rt2x00dev, 196, 0x30);
126 - rt2800_bbp_write(rt2x00dev, 195, 171);
127 - rt2800_bbp_write(rt2x00dev, 196, 0x30);
128 - }
129 -
130 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
131 rt2800_bbp_write(rt2x00dev, 75, 0x68);
132 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
133 @@ -5635,13 +5621,6 @@ void rt2800_vco_calibration(struct rt2x0
134 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
135 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
136 }
137 -
138 - /* On 11A, We should delay and wait RF/BBP to be stable
139 - * and the appropriate time should be 1000 micro seconds
140 - * 2005/06/05 - On 11G, we also need this delay time.
141 - * Otherwise it's difficult to pass the WHQL.
142 - */
143 - usleep_range(1000, 1500);
144 }
145 }
146 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
Staging tree of Christian Marangi