git.openwrt.org Git - openwrt/staging/blogic.git/blob

   1 From 9d71b0d4e30692d0d186352b494ef4e70234ca7c Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Fri, 25 Mar 2022 17:09:41 +0100
   4 Subject: [PATCH] drm/vc4: Make sure we don't end up with a core clock
   5  too high
   6
   7 Following the clock rate range improvements to the clock framework,
   8 trying to set a disjoint range on a clock will now result in an error.
   9
  10 Thus, we can't set a minimum rate higher than the maximum reported by
  11 the firmware, or clk_set_min_rate() will fail.
  12
  13 Thus we need to clamp the rate we are about to ask for to the maximum
  14 rate possible on that clock.
  15
  16 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  17 ---
  18  drivers/gpu/drm/vc4/vc4_kms.c | 14 +++++++++-----
  19  1 file changed, 9 insertions(+), 5 deletions(-)
  20
  21 --- a/drivers/gpu/drm/vc4/vc4_kms.c
  22 +++ b/drivers/gpu/drm/vc4/vc4_kms.c
  23 @@ -354,6 +354,7 @@ static void vc4_atomic_commit_tail(struc
  24         struct vc4_hvs_state *new_hvs_state;
  25         struct drm_crtc *crtc;
  26         struct vc4_hvs_state *old_hvs_state;
  27 +       unsigned long max_clock_rate = clk_get_max_rate(hvs->core_clk);
  28         unsigned int channel;
  29         int i;
  30
  31 @@ -397,8 +398,8 @@ static void vc4_atomic_commit_tail(struc
  32         if (vc4->hvs && vc4->hvs->hvs5) {
  33                 unsigned long state_rate = max(old_hvs_state->core_clock_rate,
  34                                                new_hvs_state->core_clock_rate);
  35 -               unsigned long core_rate = max_t(unsigned long,
  36 -                                               500000000, state_rate);
  37 +               unsigned long core_rate = clamp_t(unsigned long, state_rate,
  38 +                                                 500000000, max_clock_rate);
  39
  40                 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
  41         }
  42 @@ -427,10 +428,13 @@ static void vc4_atomic_commit_tail(struc
  43         drm_atomic_helper_cleanup_planes(dev, state);
  44
  45         if (vc4->hvs && vc4->hvs->hvs5) {
  46 -               drm_dbg(dev, "Running the core clock at %lu Hz\n",
  47 -                       new_hvs_state->core_clock_rate);
  48 +               unsigned long core_rate = min_t(unsigned long,
  49 +                                              max_clock_rate,
  50 +                                              new_hvs_state->core_clock_rate);
  51 +
  52 +               drm_dbg(dev, "Running the core clock at %lu Hz\n", core_rate);
  53
  54 -               WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate));
  55 +               WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
  56
  57                 drm_dbg(dev, "Core clock actual rate: %lu Hz\n",
  58                         clk_get_rate(hvs->core_clk));