git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 573eec222bc82fb5e724586267fbbb1aed9ffd03 Mon Sep 17 00:00:00 2001
   2 From: Chuanhong Guo <gch981213@gmail.com>
   3 Date: Sun, 20 Mar 2022 17:59:58 +0800
   4 Subject: [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG
   5
   6 Add support for:
   7  GD5F1GQ4RExxG
   8  GD5F2GQ4{U,R}ExxG
   9
  10 These chips differ from GD5F1GQ4UExxG only in chip ID, voltage
  11 and capacity.
  12
  13 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  14 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  15 Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-3-gch981213@gmail.com
  16 ---
  17  drivers/mtd/nand/spi/gigadevice.c | 30 ++++++++++++++++++++++++++++++
  18  1 file changed, 30 insertions(+)
  19
  20 --- a/drivers/mtd/nand/spi/gigadevice.c
  21 +++ b/drivers/mtd/nand/spi/gigadevice.c
  22 @@ -333,6 +333,36 @@ static const struct spinand_info gigadev
  23                      SPINAND_HAS_QE_BIT,
  24                      SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  25                                      gd5fxgq4uexxg_ecc_get_status)),
  26 +       SPINAND_INFO("GD5F1GQ4RExxG",
  27 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
  28 +                    NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
  29 +                    NAND_ECCREQ(8, 512),
  30 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
  31 +                                             &write_cache_variants,
  32 +                                             &update_cache_variants),
  33 +                    SPINAND_HAS_QE_BIT,
  34 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  35 +                                    gd5fxgq4uexxg_ecc_get_status)),
  36 +       SPINAND_INFO("GD5F2GQ4UExxG",
  37 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
  38 +                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
  39 +                    NAND_ECCREQ(8, 512),
  40 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
  41 +                                             &write_cache_variants,
  42 +                                             &update_cache_variants),
  43 +                    SPINAND_HAS_QE_BIT,
  44 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  45 +                                    gd5fxgq4uexxg_ecc_get_status)),
  46 +       SPINAND_INFO("GD5F2GQ4RExxG",
  47 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
  48 +                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
  49 +                    NAND_ECCREQ(8, 512),
  50 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
  51 +                                             &write_cache_variants,
  52 +                                             &update_cache_variants),
  53 +                    SPINAND_HAS_QE_BIT,
  54 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  55 +                                    gd5fxgq4uexxg_ecc_get_status)),
  56         SPINAND_INFO("GD5F1GQ4UFxxG",
  57                      SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
  58                      NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),