git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From be826ce36477e94539f5d2dfe292126dbb39b3a4 Mon Sep 17 00:00:00 2001
   2 From: Luo Jie <quic_luoj@quicinc.com>
   3 Date: Thu, 7 Nov 2024 17:50:22 +0800
   4 Subject: [PATCH 1/5] dt-bindings: clock: qcom: Add CMN PLL clock controller
   5  for IPQ SoC
   6
   7 The CMN PLL controller provides clocks to networking hardware blocks
   8 and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
   9 on-chip Wi-Fi, and produces output clocks at fixed rates. These output
  10 rates are predetermined, and are unrelated to the input clock rate.
  11 The primary purpose of CMN PLL is to supply clocks to the networking
  12 hardware such as PPE (packet process engine), PCS and the externally
  13 connected switch or PHY device. The CMN PLL block also outputs fixed
  14 rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
  15 clock supplied to GCC.
  16
  17 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  18 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
  19 ---
  20  .../bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 85 +++++++++++++++++++
  21  include/dt-bindings/clock/qcom,ipq-cmn-pll.h  | 22 +++++
  22  2 files changed, 107 insertions(+)
  23  create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
  24  create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h
  25
  26 diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
  27 new file mode 100644
  28 index 000000000000..db8a3ee56067
  29 --- /dev/null
  30 +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
  31 @@ -0,0 +1,85 @@
  32 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  33 +%YAML 1.2
  34 +---
  35 +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
  36 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  37 +
  38 +title: Qualcomm CMN PLL Clock Controller on IPQ SoC
  39 +
  40 +maintainers:
  41 +  - Bjorn Andersson <andersson@kernel.org>
  42 +  - Luo Jie <quic_luoj@quicinc.com>
  43 +
  44 +description:
  45 +  The CMN (or common) PLL clock controller expects a reference
  46 +  input clock. This reference clock is from the on-board Wi-Fi.
  47 +  The CMN PLL supplies a number of fixed rate output clocks to
  48 +  the devices providing networking functions and to GCC. These
  49 +  networking hardware include PPE (packet process engine), PCS
  50 +  and the externally connected switch or PHY devices. The CMN
  51 +  PLL block also outputs fixed rate clocks to GCC. The PLL's
  52 +  primary function is to enable fixed rate output clocks for
  53 +  networking hardware functions used with the IPQ SoC.
  54 +
  55 +properties:
  56 +  compatible:
  57 +    enum:
  58 +      - qcom,ipq9574-cmn-pll
  59 +
  60 +  reg:
  61 +    maxItems: 1
  62 +
  63 +  clocks:
  64 +    items:
  65 +      - description: The reference clock. The supported clock rates include
  66 +          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
  67 +      - description: The AHB clock
  68 +      - description: The SYS clock
  69 +    description:
  70 +      The reference clock is the source clock of CMN PLL, which is from the
  71 +      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
  72 +      clock registers.
  73 +
  74 +  clock-names:
  75 +    items:
  76 +      - const: ref
  77 +      - const: ahb
  78 +      - const: sys
  79 +
  80 +  "#clock-cells":
  81 +    const: 1
  82 +
  83 +  assigned-clocks:
  84 +    maxItems: 1
  85 +
  86 +  assigned-clock-rates-u64:
  87 +    maxItems: 1
  88 +
  89 +required:
  90 +  - compatible
  91 +  - reg
  92 +  - clocks
  93 +  - clock-names
  94 +  - "#clock-cells"
  95 +  - assigned-clocks
  96 +  - assigned-clock-rates-u64
  97 +
  98 +additionalProperties: false
  99 +
 100 +examples:
 101 +  - |
 102 +    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
 103 +    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
 104 +
 105 +    cmn_pll: clock-controller@9b000 {
 106 +        compatible = "qcom,ipq9574-cmn-pll";
 107 +        reg = <0x0009b000 0x800>;
 108 +        clocks = <&cmn_pll_ref_clk>,
 109 +                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
 110 +                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
 111 +        clock-names = "ref", "ahb", "sys";
 112 +        #clock-cells = <1>;
 113 +        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
 114 +        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
 115 +    };
 116 +...
 117 diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
 118 new file mode 100644
 119 index 000000000000..936e92b3b62c
 120 --- /dev/null
 121 +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
 122 @@ -0,0 +1,22 @@
 123 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 124 +/*
 125 + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 126 + */
 127 +
 128 +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
 129 +#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
 130 +
 131 +/* CMN PLL core clock. */
 132 +#define CMN_PLL_CLK                    0
 133 +
 134 +/* The output clocks from CMN PLL of IPQ9574. */
 135 +#define XO_24MHZ_CLK                   1
 136 +#define SLEEP_32KHZ_CLK                        2
 137 +#define PCS_31P25MHZ_CLK               3
 138 +#define NSS_1200MHZ_CLK                        4
 139 +#define PPE_353MHZ_CLK                 5
 140 +#define ETH0_50MHZ_CLK                 6
 141 +#define ETH1_50MHZ_CLK                 7
 142 +#define ETH2_50MHZ_CLK                 8
 143 +#define ETH_25MHZ_CLK                  9
 144 +#endif
 145 --
 146 2.45.2
 147