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1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
2 Subject: [PATCH 1/2] net: phy: cherry-pick Broadcom drivers updates from
3 v4.10-rc1
4
5 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
6 ---
7
8 --- a/drivers/net/phy/broadcom.c
9 +++ b/drivers/net/phy/broadcom.c
10 @@ -18,7 +18,7 @@
11 #include <linux/module.h>
12 #include <linux/phy.h>
13 #include <linux/brcmphy.h>
14 -
15 +#include <linux/of.h>
16
17 #define BRCM_PHY_MODEL(phydev) \
18 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
19 @@ -30,9 +30,32 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
20 MODULE_AUTHOR("Maciej W. Rozycki");
21 MODULE_LICENSE("GPL");
22
23 -static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
24 +static int bcm54810_config(struct phy_device *phydev)
25 {
26 - return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
27 + int rc, val;
28 +
29 + val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
30 + val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
31 + rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
32 + val);
33 + if (rc < 0)
34 + return rc;
35 +
36 + val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
37 + val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
38 + val |= MII_BCM54XX_AUXCTL_MISC_WREN;
39 + rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
40 + val);
41 + if (rc < 0)
42 + return rc;
43 +
44 + val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
45 + val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
46 + rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
47 + if (rc < 0)
48 + return rc;
49 +
50 + return 0;
51 }
52
53 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
54 @@ -207,6 +230,12 @@ static int bcm54xx_config_init(struct ph
55 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
56 bcm54xx_adjust_rxrefclk(phydev);
57
58 + if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
59 + err = bcm54810_config(phydev);
60 + if (err)
61 + return err;
62 + }
63 +
64 bcm54xx_phydsp_config(phydev);
65
66 return 0;
67 @@ -304,6 +333,7 @@ static int bcm5482_read_status(struct ph
68
69 static int bcm5481_config_aneg(struct phy_device *phydev)
70 {
71 + struct device_node *np = phydev->dev.of_node;
72 int ret;
73
74 /* Aneg firsly. */
75 @@ -334,6 +364,49 @@ static int bcm5481_config_aneg(struct ph
76 phy_write(phydev, 0x18, reg);
77 }
78
79 + if (of_property_read_bool(np, "enet-phy-lane-swap")) {
80 + /* Lane Swap - Undocumented register...magic! */
81 + ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
82 + 0x11B);
83 + if (ret < 0)
84 + return ret;
85 + }
86 +
87 + return ret;
88 +}
89 +
90 +static int bcm54612e_config_aneg(struct phy_device *phydev)
91 +{
92 + int ret;
93 +
94 + /* First, auto-negotiate. */
95 + ret = genphy_config_aneg(phydev);
96 +
97 + /* Clear TX internal delay unless requested. */
98 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
99 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
100 + /* Disable TXD to GTXCLK clock delay (default set) */
101 + /* Bit 9 is the only field in shadow register 00011 */
102 + bcm_phy_write_shadow(phydev, 0x03, 0);
103 + }
104 +
105 + /* Clear RX internal delay unless requested. */
106 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
107 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
108 + u16 reg;
109 +
110 + /* Errata: reads require filling in the write selector field */
111 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
112 + MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
113 + reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
114 + /* Disable RXD to RXC delay (default set) */
115 + reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
116 + /* Clear shadow selector field */
117 + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
118 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
119 + MII_BCM54XX_AUXCTL_MISC_WREN | reg);
120 + }
121 +
122 return ret;
123 }
124
125 @@ -488,6 +561,19 @@ static struct phy_driver broadcom_driver
126 .config_intr = bcm_phy_config_intr,
127 .driver = { .owner = THIS_MODULE },
128 }, {
129 + .phy_id = PHY_ID_BCM54612E,
130 + .phy_id_mask = 0xfffffff0,
131 + .name = "Broadcom BCM54612E",
132 + .features = PHY_GBIT_FEATURES |
133 + SUPPORTED_Pause | SUPPORTED_Asym_Pause,
134 + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
135 + .config_init = bcm54xx_config_init,
136 + .config_aneg = bcm54612e_config_aneg,
137 + .read_status = genphy_read_status,
138 + .ack_interrupt = bcm_phy_ack_intr,
139 + .config_intr = bcm_phy_config_intr,
140 + .driver = { .owner = THIS_MODULE },
141 +}, {
142 .phy_id = PHY_ID_BCM54616S,
143 .phy_id_mask = 0xfffffff0,
144 .name = "Broadcom BCM54616S",
145 @@ -527,6 +613,19 @@ static struct phy_driver broadcom_driver
146 .config_intr = bcm_phy_config_intr,
147 .driver = { .owner = THIS_MODULE },
148 }, {
149 + .phy_id = PHY_ID_BCM54810,
150 + .phy_id_mask = 0xfffffff0,
151 + .name = "Broadcom BCM54810",
152 + .features = PHY_GBIT_FEATURES |
153 + SUPPORTED_Pause | SUPPORTED_Asym_Pause,
154 + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
155 + .config_init = bcm54xx_config_init,
156 + .config_aneg = bcm5481_config_aneg,
157 + .read_status = genphy_read_status,
158 + .ack_interrupt = bcm_phy_ack_intr,
159 + .config_intr = bcm_phy_config_intr,
160 + .driver = { .owner = THIS_MODULE },
161 +}, {
162 .phy_id = PHY_ID_BCM5482,
163 .phy_id_mask = 0xfffffff0,
164 .name = "Broadcom BCM5482",
165 @@ -612,9 +711,11 @@ static struct mdio_device_id __maybe_unu
166 { PHY_ID_BCM5411, 0xfffffff0 },
167 { PHY_ID_BCM5421, 0xfffffff0 },
168 { PHY_ID_BCM5461, 0xfffffff0 },
169 + { PHY_ID_BCM54612E, 0xfffffff0 },
170 { PHY_ID_BCM54616S, 0xfffffff0 },
171 { PHY_ID_BCM5464, 0xfffffff0 },
172 { PHY_ID_BCM5481, 0xfffffff0 },
173 + { PHY_ID_BCM54810, 0xfffffff0 },
174 { PHY_ID_BCM5482, 0xfffffff0 },
175 { PHY_ID_BCM50610, 0xfffffff0 },
176 { PHY_ID_BCM50610M, 0xfffffff0 },
177 --- a/include/linux/brcmphy.h
178 +++ b/include/linux/brcmphy.h
179 @@ -13,11 +13,13 @@
180 #define PHY_ID_BCM5241 0x0143bc30
181 #define PHY_ID_BCMAC131 0x0143bc70
182 #define PHY_ID_BCM5481 0x0143bca0
183 +#define PHY_ID_BCM54810 0x03625d00
184 #define PHY_ID_BCM5482 0x0143bcb0
185 #define PHY_ID_BCM5411 0x00206070
186 #define PHY_ID_BCM5421 0x002060e0
187 #define PHY_ID_BCM5464 0x002060b0
188 #define PHY_ID_BCM5461 0x002060c0
189 +#define PHY_ID_BCM54612E 0x03625e60
190 #define PHY_ID_BCM54616S 0x03625d10
191 #define PHY_ID_BCM57780 0x03625d90
192
193 @@ -52,6 +54,7 @@
194 #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
195 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
196 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
197 +
198 /* Broadcom BCM7xxx specific workarounds */
199 #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
200 #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
201 @@ -102,11 +105,14 @@
202 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
203
204 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
205 +#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
206 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
207 #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
208 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
209 +#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
210 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
211
212 -#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
213 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
214
215 /*
216 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
217 @@ -186,6 +192,12 @@
218 #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
219 #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
220
221 +/* BCM54810 Registers */
222 +#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
223 +#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
224 +#define BCM54810_SHD_CLK_CTL 0x3
225 +#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
226 +
227
228 /*****************************************************************************/
229 /* Fast Ethernet Transceiver definitions. */
230 --- a/drivers/net/phy/Kconfig
231 +++ b/drivers/net/phy/Kconfig
232 @@ -77,7 +77,7 @@ config BROADCOM_PHY
233 select BCM_NET_PHYLIB
234 ---help---
235 Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
236 - BCM5481 and BCM5482 PHYs.
237 + BCM5481, BCM54810 and BCM5482 PHYs.
238
239 config BCM_CYGNUS_PHY
240 tristate "Drivers for Broadcom Cygnus SoC internal PHY"
241 --- a/drivers/net/phy/bcm-phy-lib.c
242 +++ b/drivers/net/phy/bcm-phy-lib.c
243 @@ -50,6 +50,23 @@ int bcm_phy_read_exp(struct phy_device *
244 }
245 EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
246
247 +int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
248 +{
249 + /* The register must be written to both the Shadow Register Select and
250 + * the Shadow Read Register Selector
251 + */
252 + phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
253 + regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
254 + return phy_read(phydev, MII_BCM54XX_AUX_CTL);
255 +}
256 +EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
257 +
258 +int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
259 +{
260 + return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
261 +}
262 +EXPORT_SYMBOL(bcm54xx_auxctl_write);
263 +
264 int bcm_phy_write_misc(struct phy_device *phydev,
265 u16 reg, u16 chl, u16 val)
266 {
267 --- a/drivers/net/phy/bcm-phy-lib.h
268 +++ b/drivers/net/phy/bcm-phy-lib.h
269 @@ -19,6 +19,9 @@
270 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
271 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
272
273 +int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val);
274 +int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum);
275 +
276 int bcm_phy_write_misc(struct phy_device *phydev,
277 u16 reg, u16 chl, u16 value);
278 int bcm_phy_read_misc(struct phy_device *phydev,
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