projects / openwrt / staging / 981213.git / blob
? search:


110944658dee8088114834bf082cd0d22063662c
[openwrt/staging/981213.git] /
1 From 2a3ec7ae313310c1092e4256208cc04d1958e469 Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Sun, 19 Mar 2023 12:58:02 +0000
4 Subject: [PATCH] net: ethernet: mtk_eth_soc: switch to external PCS driver
5
6 Now that we got a PCS driver, use it and remove the now redundant
7 PCS code and it's header macros from the Ethernet driver.
8
9 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
10 Tested-by: Frank Wunderlich <frank-w@public-files.de>
11 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
13 ---
14 drivers/net/ethernet/mediatek/Kconfig | 2 +
15 drivers/net/ethernet/mediatek/Makefile | 2 +-
16 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 61 +++++-
17 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 93 +--------
18 drivers/net/ethernet/mediatek/mtk_sgmii.c | 217 --------------------
19 5 files changed, 56 insertions(+), 319 deletions(-)
20 delete mode 100644 drivers/net/ethernet/mediatek/mtk_sgmii.c
21
22 --- a/drivers/net/ethernet/mediatek/Kconfig
23 +++ b/drivers/net/ethernet/mediatek/Kconfig
24 @@ -19,6 +19,8 @@ config NET_MEDIATEK_SOC
25 select DIMLIB
26 select PAGE_POOL
27 select PAGE_POOL_STATS
28 + select PCS_MTK_LYNXI
29 + select REGMAP_MMIO
30 help
31 This driver supports the gigabit ethernet MACs in the
32 MediaTek SoC family.
33 --- a/drivers/net/ethernet/mediatek/Makefile
34 +++ b/drivers/net/ethernet/mediatek/Makefile
35 @@ -4,7 +4,7 @@
36 #
37
38 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
39 -mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
40 +mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
41 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
42 ifdef CONFIG_DEBUG_FS
43 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
44 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
45 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
46 @@ -20,6 +20,7 @@
47 #include <linux/interrupt.h>
48 #include <linux/pinctrl/devinfo.h>
49 #include <linux/phylink.h>
50 +#include <linux/pcs/pcs-mtk-lynxi.h>
51 #include <linux/jhash.h>
52 #include <linux/bitfield.h>
53 #include <net/dsa.h>
54 @@ -400,7 +401,7 @@ static struct phylink_pcs *mtk_mac_selec
55 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
56 0 : mac->id;
57
58 - return mtk_sgmii_select_pcs(eth->sgmii, sid);
59 + return eth->sgmii_pcs[sid];
60 }
61
62 return NULL;
63 @@ -4016,8 +4017,17 @@ static int mtk_unreg_dev(struct mtk_eth
64 return 0;
65 }
66
67 +static void mtk_sgmii_destroy(struct mtk_eth *eth)
68 +{
69 + int i;
70 +
71 + for (i = 0; i < MTK_MAX_DEVS; i++)
72 + mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]);
73 +}
74 +
75 static int mtk_cleanup(struct mtk_eth *eth)
76 {
77 + mtk_sgmii_destroy(eth);
78 mtk_unreg_dev(eth);
79 mtk_free_dev(eth);
80 cancel_work_sync(&eth->pending_work);
81 @@ -4457,6 +4467,36 @@ void mtk_eth_set_dma_device(struct mtk_e
82 rtnl_unlock();
83 }
84
85 +static int mtk_sgmii_init(struct mtk_eth *eth)
86 +{
87 + struct device_node *np;
88 + struct regmap *regmap;
89 + u32 flags;
90 + int i;
91 +
92 + for (i = 0; i < MTK_MAX_DEVS; i++) {
93 + np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i);
94 + if (!np)
95 + break;
96 +
97 + regmap = syscon_node_to_regmap(np);
98 + flags = 0;
99 + if (of_property_read_bool(np, "mediatek,pnswap"))
100 + flags |= MTK_SGMII_FLAG_PN_SWAP;
101 +
102 + of_node_put(np);
103 +
104 + if (IS_ERR(regmap))
105 + return PTR_ERR(regmap);
106 +
107 + eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap,
108 + eth->soc->ana_rgc3,
109 + flags);
110 + }
111 +
112 + return 0;
113 +}
114 +
115 static int mtk_probe(struct platform_device *pdev)
116 {
117 struct resource *res = NULL;
118 @@ -4520,13 +4560,7 @@ static int mtk_probe(struct platform_dev
119 }
120
121 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
122 - eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
123 - GFP_KERNEL);
124 - if (!eth->sgmii)
125 - return -ENOMEM;
126 -
127 - err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
128 - eth->soc->ana_rgc3);
129 + err = mtk_sgmii_init(eth);
130
131 if (err)
132 return err;
133 @@ -4537,14 +4571,17 @@ static int mtk_probe(struct platform_dev
134 "mediatek,pctl");
135 if (IS_ERR(eth->pctl)) {
136 dev_err(&pdev->dev, "no pctl regmap found\n");
137 - return PTR_ERR(eth->pctl);
138 + err = PTR_ERR(eth->pctl);
139 + goto err_destroy_sgmii;
140 }
141 }
142
143 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
144 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
145 - if (!res)
146 - return -EINVAL;
147 + if (!res) {
148 + err = -EINVAL;
149 + goto err_destroy_sgmii;
150 + }
151 }
152
153 if (eth->soc->offload_version) {
154 @@ -4703,6 +4740,8 @@ err_deinit_hw:
155 mtk_hw_deinit(eth);
156 err_wed_exit:
157 mtk_wed_exit();
158 +err_destroy_sgmii:
159 + mtk_sgmii_destroy(eth);
160
161 return err;
162 }
163 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
164 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
165 @@ -510,65 +510,6 @@
166 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
167 #define ETHSYS_DMA_AG_MAP_PPE BIT(2)
168
169 -/* SGMII subsystem config registers */
170 -/* BMCR (low 16) BMSR (high 16) */
171 -#define SGMSYS_PCS_CONTROL_1 0x0
172 -#define SGMII_BMCR GENMASK(15, 0)
173 -#define SGMII_BMSR GENMASK(31, 16)
174 -#define SGMII_AN_RESTART BIT(9)
175 -#define SGMII_ISOLATE BIT(10)
176 -#define SGMII_AN_ENABLE BIT(12)
177 -#define SGMII_LINK_STATYS BIT(18)
178 -#define SGMII_AN_ABILITY BIT(19)
179 -#define SGMII_AN_COMPLETE BIT(21)
180 -#define SGMII_PCS_FAULT BIT(23)
181 -#define SGMII_AN_EXPANSION_CLR BIT(30)
182 -
183 -#define SGMSYS_PCS_ADVERTISE 0x8
184 -#define SGMII_ADVERTISE GENMASK(15, 0)
185 -#define SGMII_LPA GENMASK(31, 16)
186 -
187 -/* Register to programmable link timer, the unit in 2 * 8ns */
188 -#define SGMSYS_PCS_LINK_TIMER 0x18
189 -#define SGMII_LINK_TIMER_MASK GENMASK(19, 0)
190 -#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & SGMII_LINK_TIMER_MASK)
191 -
192 -/* Register to control remote fault */
193 -#define SGMSYS_SGMII_MODE 0x20
194 -#define SGMII_IF_MODE_SGMII BIT(0)
195 -#define SGMII_SPEED_DUPLEX_AN BIT(1)
196 -#define SGMII_SPEED_MASK GENMASK(3, 2)
197 -#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
198 -#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1)
199 -#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
200 -#define SGMII_DUPLEX_HALF BIT(4)
201 -#define SGMII_IF_MODE_BIT5 BIT(5)
202 -#define SGMII_REMOTE_FAULT_DIS BIT(8)
203 -#define SGMII_CODE_SYNC_SET_VAL BIT(9)
204 -#define SGMII_CODE_SYNC_SET_EN BIT(10)
205 -#define SGMII_SEND_AN_ERROR_EN BIT(11)
206 -#define SGMII_IF_MODE_MASK GENMASK(5, 1)
207 -
208 -/* Register to reset SGMII design */
209 -#define SGMII_RESERVED_0 0x34
210 -#define SGMII_SW_RESET BIT(0)
211 -
212 -/* Register to set SGMII speed, ANA RG_ Control Signals III*/
213 -#define SGMSYS_ANA_RG_CS3 0x2028
214 -#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
215 -#define RG_PHY_SPEED_1_25G 0x0
216 -#define RG_PHY_SPEED_3_125G BIT(2)
217 -
218 -/* Register to power up QPHY */
219 -#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
220 -#define SGMII_PHYA_PWD BIT(4)
221 -
222 -/* Register to QPHY wrapper control */
223 -#define SGMSYS_QPHY_WRAP_CTRL 0xec
224 -#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
225 -#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
226 -#define MTK_SGMII_FLAG_PN_SWAP BIT(0)
227 -
228 /* Infrasys subsystem config registers */
229 #define INFRA_MISC2 0x70c
230 #define CO_QPHY_SEL BIT(0)
231 @@ -1102,31 +1043,6 @@ struct mtk_soc_data {
232 /* currently no SoC has more than 2 macs */
233 #define MTK_MAX_DEVS 2
234
235 -/* struct mtk_pcs - This structure holds each sgmii regmap and associated
236 - * data
237 - * @regmap: The register map pointing at the range used to setup
238 - * SGMII modes
239 - * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
240 - * @interface: Currently configured interface mode
241 - * @pcs: Phylink PCS structure
242 - * @flags: Flags indicating hardware properties
243 - */
244 -struct mtk_pcs {
245 - struct regmap *regmap;
246 - u32 ana_rgc3;
247 - phy_interface_t interface;
248 - struct phylink_pcs pcs;
249 - u32 flags;
250 -};
251 -
252 -/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
253 - * characteristics
254 - * @pcs Array of individual PCS structures
255 - */
256 -struct mtk_sgmii {
257 - struct mtk_pcs pcs[MTK_MAX_DEVS];
258 -};
259 -
260 /* struct mtk_eth - This is the main datasructure for holding the state
261 * of the driver
262 * @dev: The device pointer
263 @@ -1146,6 +1062,7 @@ struct mtk_sgmii {
264 * MII modes
265 * @infra: The register map pointing at the range used to setup
266 * SGMII and GePHY path
267 + * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
268 * @pctl: The register map pointing at the range used to setup
269 * GMAC port drive/slew values
270 * @dma_refcnt: track how many netdevs are using the DMA engine
271 @@ -1186,8 +1103,8 @@ struct mtk_eth {
272 u32 msg_enable;
273 unsigned long sysclk;
274 struct regmap *ethsys;
275 - struct regmap *infra;
276 - struct mtk_sgmii *sgmii;
277 + struct regmap *infra;
278 + struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS];
279 struct regmap *pctl;
280 bool hwlro;
281 refcount_t dma_refcnt;
282 @@ -1349,10 +1266,6 @@ void mtk_stats_update_mac(struct mtk_mac
283 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
284 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
285
286 -struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id);
287 -int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
288 - u32 ana_rgc3);
289 -
290 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
291 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
292 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
293 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
294 +++ /dev/null
295 @@ -1,217 +0,0 @@
296 -// SPDX-License-Identifier: GPL-2.0
297 -// Copyright (c) 2018-2019 MediaTek Inc.
298 -
299 -/* A library for MediaTek SGMII circuit
300 - *
301 - * Author: Sean Wang <sean.wang@mediatek.com>
302 - *
303 - */
304 -
305 -#include <linux/mfd/syscon.h>
306 -#include <linux/of.h>
307 -#include <linux/phylink.h>
308 -#include <linux/regmap.h>
309 -
310 -#include "mtk_eth_soc.h"
311 -
312 -static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs)
313 -{
314 - return container_of(pcs, struct mtk_pcs, pcs);
315 -}
316 -
317 -static void mtk_pcs_get_state(struct phylink_pcs *pcs,
318 - struct phylink_link_state *state)
319 -{
320 - struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
321 - unsigned int bm, adv;
322 -
323 - /* Read the BMSR and LPA */
324 - regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm);
325 - regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
326 -
327 - phylink_mii_c22_pcs_decode_state(state, FIELD_GET(SGMII_BMSR, bm),
328 - FIELD_GET(SGMII_LPA, adv));
329 -}
330 -
331 -static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
332 - phy_interface_t interface,
333 - const unsigned long *advertising,
334 - bool permit_pause_to_mac)
335 -{
336 - bool mode_changed = false, changed, use_an;
337 - struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
338 - unsigned int rgc3, sgm_mode, bmcr;
339 - int advertise, link_timer;
340 -
341 - advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
342 - advertising);
343 - if (advertise < 0)
344 - return advertise;
345 -
346 - /* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and
347 - * we assume that fixes it's speed at bitrate = line rate (in
348 - * other words, 1000Mbps or 2500Mbps).
349 - */
350 - if (interface == PHY_INTERFACE_MODE_SGMII) {
351 - sgm_mode = SGMII_IF_MODE_SGMII;
352 - if (phylink_autoneg_inband(mode)) {
353 - sgm_mode |= SGMII_REMOTE_FAULT_DIS |
354 - SGMII_SPEED_DUPLEX_AN;
355 - use_an = true;
356 - } else {
357 - use_an = false;
358 - }
359 - } else if (phylink_autoneg_inband(mode)) {
360 - /* 1000base-X or 2500base-X autoneg */
361 - sgm_mode = SGMII_REMOTE_FAULT_DIS;
362 - use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
363 - advertising);
364 - } else {
365 - /* 1000base-X or 2500base-X without autoneg */
366 - sgm_mode = 0;
367 - use_an = false;
368 - }
369 -
370 - if (use_an) {
371 - bmcr = SGMII_AN_ENABLE;
372 - } else {
373 - bmcr = 0;
374 - }
375 -
376 - if (mpcs->interface != interface) {
377 - link_timer = phylink_get_link_timer_ns(interface);
378 - if (link_timer < 0)
379 - return link_timer;
380 -
381 - /* PHYA power down */
382 - regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
383 - SGMII_PHYA_PWD, SGMII_PHYA_PWD);
384 -
385 - if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
386 - regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
387 - SGMII_PN_SWAP_MASK,
388 - SGMII_PN_SWAP_TX_RX);
389 -
390 - /* Reset SGMII PCS state */
391 - regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
392 - SGMII_SW_RESET, SGMII_SW_RESET);
393 -
394 - if (interface == PHY_INTERFACE_MODE_2500BASEX)
395 - rgc3 = RG_PHY_SPEED_3_125G;
396 - else
397 - rgc3 = 0;
398 -
399 - /* Configure the underlying interface speed */
400 - regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
401 - RG_PHY_SPEED_3_125G, rgc3);
402 -
403 - /* Setup the link timer */
404 - regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8);
405 -
406 - mpcs->interface = interface;
407 - mode_changed = true;
408 - }
409 -
410 - /* Update the advertisement, noting whether it has changed */
411 - regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
412 - SGMII_ADVERTISE, advertise, &changed);
413 -
414 - /* Update the sgmsys mode register */
415 - regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
416 - SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN |
417 - SGMII_IF_MODE_SGMII, sgm_mode);
418 -
419 - /* Update the BMCR */
420 - regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
421 - SGMII_AN_ENABLE, bmcr);
422 -
423 - /* Release PHYA power down state
424 - * Only removing bit SGMII_PHYA_PWD isn't enough.
425 - * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
426 - * prevents SGMII from working. The SGMII still shows link but no traffic
427 - * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
428 - * taken from a good working state of the SGMII interface.
429 - * Unknown how much the QPHY needs but it is racy without a sleep.
430 - * Tested on mt7622 & mt7986.
431 - */
432 - usleep_range(50, 100);
433 - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
434 -
435 - return changed || mode_changed;
436 -}
437 -
438 -static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
439 -{
440 - struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
441 -
442 - regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
443 - SGMII_AN_RESTART, SGMII_AN_RESTART);
444 -}
445 -
446 -static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
447 - phy_interface_t interface, int speed, int duplex)
448 -{
449 - struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
450 - unsigned int sgm_mode;
451 -
452 - if (!phylink_autoneg_inband(mode)) {
453 - /* Force the speed and duplex setting */
454 - if (speed == SPEED_10)
455 - sgm_mode = SGMII_SPEED_10;
456 - else if (speed == SPEED_100)
457 - sgm_mode = SGMII_SPEED_100;
458 - else
459 - sgm_mode = SGMII_SPEED_1000;
460 -
461 - if (duplex != DUPLEX_FULL)
462 - sgm_mode |= SGMII_DUPLEX_HALF;
463 -
464 - regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
465 - SGMII_DUPLEX_HALF | SGMII_SPEED_MASK,
466 - sgm_mode);
467 - }
468 -}
469 -
470 -static const struct phylink_pcs_ops mtk_pcs_ops = {
471 - .pcs_get_state = mtk_pcs_get_state,
472 - .pcs_config = mtk_pcs_config,
473 - .pcs_an_restart = mtk_pcs_restart_an,
474 - .pcs_link_up = mtk_pcs_link_up,
475 -};
476 -
477 -int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
478 -{
479 - struct device_node *np;
480 - int i;
481 -
482 - for (i = 0; i < MTK_MAX_DEVS; i++) {
483 - np = of_parse_phandle(r, "mediatek,sgmiisys", i);
484 - if (!np)
485 - break;
486 -
487 - ss->pcs[i].ana_rgc3 = ana_rgc3;
488 - ss->pcs[i].regmap = syscon_node_to_regmap(np);
489 -
490 - ss->pcs[i].flags = 0;
491 - if (of_property_read_bool(np, "mediatek,pnswap"))
492 - ss->pcs[i].flags |= MTK_SGMII_FLAG_PN_SWAP;
493 -
494 - of_node_put(np);
495 - if (IS_ERR(ss->pcs[i].regmap))
496 - return PTR_ERR(ss->pcs[i].regmap);
497 -
498 - ss->pcs[i].pcs.ops = &mtk_pcs_ops;
499 - ss->pcs[i].pcs.poll = true;
500 - ss->pcs[i].interface = PHY_INTERFACE_MODE_NA;
501 - }
502 -
503 - return 0;
504 -}
505 -
506 -struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id)
507 -{
508 - if (!ss->pcs[id].regmap)
509 - return NULL;
510 -
511 - return &ss->pcs[id].pcs;
512 -}
Staging tree of Chuanhong Guo