git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 64eca7ad058cff861b48cdead8dee40dfc284e9e Mon Sep 17 00:00:00 2001
   2 From: William Zhang <william.zhang@broadcom.com>
   3 Date: Wed, 8 Jun 2022 11:04:36 -0700
   4 Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6856
   5
   6 Add DTS for ARMv8 based broadband SoC BCM6856. bcm6856.dtsi is the
   7 SoC description DTS header and bcm96856.dts is a simple DTS file for
   8 Broadcom BCM96956 Reference board that only enable the UART port.
   9
  10 Signed-off-by: William Zhang <william.zhang@broadcom.com>
  11 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  12 ---
  13  arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
  14  .../boot/dts/broadcom/bcmbca/bcm6856.dtsi     | 103 ++++++++++++++++++
  15  .../boot/dts/broadcom/bcmbca/bcm96856.dts     |  30 +++++
  16  3 files changed, 135 insertions(+), 1 deletion(-)
  17  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
  18  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
  19
  20 --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  21 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  22 @@ -2,4 +2,5 @@
  23  dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
  24                                 bcm963158.dtb \
  25                                 bcm96858.dtb \
  26 -                               bcm963146.dtb
  27 +                               bcm963146.dtb \
  28 +                               bcm96856.dtb
  29 --- /dev/null
  30 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
  31 @@ -0,0 +1,103 @@
  32 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  33 +/*
  34 + * Copyright 2022 Broadcom Ltd.
  35 + */
  36 +
  37 +#include <dt-bindings/interrupt-controller/irq.h>
  38 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  39 +
  40 +/ {
  41 +       compatible = "brcm,bcm6856", "brcm,bcmbca";
  42 +       #address-cells = <2>;
  43 +       #size-cells = <2>;
  44 +
  45 +       interrupt-parent = <&gic>;
  46 +
  47 +       cpus {
  48 +               #address-cells = <2>;
  49 +               #size-cells = <0>;
  50 +
  51 +               B53_0: cpu@0 {
  52 +                       compatible = "brcm,brahma-b53";
  53 +                       device_type = "cpu";
  54 +                       reg = <0x0 0x0>;
  55 +                       next-level-cache = <&L2_0>;
  56 +                       enable-method = "psci";
  57 +               };
  58 +
  59 +               B53_1: cpu@1 {
  60 +                       compatible = "brcm,brahma-b53";
  61 +                       device_type = "cpu";
  62 +                       reg = <0x0 0x1>;
  63 +                       next-level-cache = <&L2_0>;
  64 +                       enable-method = "psci";
  65 +               };
  66 +
  67 +               L2_0: l2-cache0 {
  68 +                       compatible = "cache";
  69 +               };
  70 +       };
  71 +
  72 +       timer {
  73 +               compatible = "arm,armv8-timer";
  74 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  75 +                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  76 +                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  77 +                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  78 +       };
  79 +
  80 +       pmu: pmu {
  81 +               compatible = "arm,cortex-a53-pmu";
  82 +               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  83 +                       <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  84 +               interrupt-affinity = <&B53_0>, <&B53_1>;
  85 +       };
  86 +
  87 +       clocks: clocks {
  88 +               periph_clk:periph-clk {
  89 +                       compatible = "fixed-clock";
  90 +                       #clock-cells = <0>;
  91 +                       clock-frequency = <200000000>;
  92 +               };
  93 +       };
  94 +
  95 +       psci {
  96 +               compatible = "arm,psci-0.2";
  97 +               method = "smc";
  98 +       };
  99 +
 100 +       axi@81000000 {
 101 +               compatible = "simple-bus";
 102 +               #address-cells = <1>;
 103 +               #size-cells = <1>;
 104 +               ranges = <0x0 0x0 0x81000000 0x8000>;
 105 +
 106 +               gic: interrupt-controller@1000 {
 107 +                       compatible = "arm,gic-400";
 108 +                       #interrupt-cells = <3>;
 109 +                       interrupt-controller;
 110 +                       reg = <0x1000 0x1000>, /* GICD */
 111 +                               <0x2000 0x2000>, /* GICC */
 112 +                               <0x4000 0x2000>, /* GICH */
 113 +                               <0x6000 0x2000>; /* GICV */
 114 +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
 115 +                                       IRQ_TYPE_LEVEL_HIGH)>;
 116 +               };
 117 +       };
 118 +
 119 +       bus@ff800000 {
 120 +               compatible = "simple-bus";
 121 +               #address-cells = <1>;
 122 +               #size-cells = <1>;
 123 +               ranges = <0x0 0x0 0xff800000 0x800000>;
 124 +
 125 +               uart0: serial@640 {
 126 +                       compatible = "brcm,bcm6345-uart";
 127 +                       reg = <0x640 0x18>;
 128 +                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 129 +                       clocks = <&periph_clk>;
 130 +                       clock-names = "refclk";
 131 +                       status = "disabled";
 132 +               };
 133 +       };
 134 +};
 135 --- /dev/null
 136 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
 137 @@ -0,0 +1,30 @@
 138 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 139 +/*
 140 + * Copyright 2022 Broadcom Ltd.
 141 + */
 142 +
 143 +/dts-v1/;
 144 +
 145 +#include "bcm6856.dtsi"
 146 +
 147 +/ {
 148 +       model = "Broadcom BCM96856 Reference Board";
 149 +       compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
 150 +
 151 +       aliases {
 152 +               serial0 = &uart0;
 153 +       };
 154 +
 155 +       chosen {
 156 +               stdout-path = "serial0:115200n8";
 157 +       };
 158 +
 159 +       memory@0 {
 160 +               device_type = "memory";
 161 +               reg = <0x0 0x0 0x0 0x08000000>;
 162 +       };
 163 +};
 164 +
 165 +&uart0 {
 166 +       status = "okay";
 167 +};