git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 29be47fcd6a06ea2e79eeeca6e69ad1e23254a69 Mon Sep 17 00:00:00 2001
   2 From: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
   3 Date: Sat, 24 Feb 2024 11:45:11 +0000
   4 Subject: [PATCH] nvmem: zynqmp_nvmem: zynqmp_nvmem_probe cleanup
   5
   6 - Remove static nvmem_config declaration
   7 - Remove zynqmp_nvmem_data
   8
   9 Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
  10 Acked-by: Kalyani Akula <Kalyani.akula@amd.com>
  11 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
  12 Link: https://lore.kernel.org/r/20240224114516.86365-7-srinivas.kandagatla@linaro.org
  13 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  14 ---
  15  drivers/nvmem/zynqmp_nvmem.c | 37 ++++++++++++------------------------
  16  1 file changed, 12 insertions(+), 25 deletions(-)
  17
  18 --- a/drivers/nvmem/zynqmp_nvmem.c
  19 +++ b/drivers/nvmem/zynqmp_nvmem.c
  20 @@ -1,6 +1,7 @@
  21  // SPDX-License-Identifier: GPL-2.0+
  22  /*
  23   * Copyright (C) 2019 Xilinx, Inc.
  24 + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
  25   */
  26
  27  #include <linux/module.h>
  28 @@ -11,36 +12,25 @@
  29
  30  #define SILICON_REVISION_MASK 0xF
  31
  32 -struct zynqmp_nvmem_data {
  33 -       struct device *dev;
  34 -       struct nvmem_device *nvmem;
  35 -};
  36
  37  static int zynqmp_nvmem_read(void *context, unsigned int offset,
  38                              void *val, size_t bytes)
  39  {
  40 +       struct device *dev = context;
  41         int ret;
  42 -       int idcode, version;
  43 -       struct zynqmp_nvmem_data *priv = context;
  44 +       int idcode;
  45 +       int version;
  46
  47         ret = zynqmp_pm_get_chipid(&idcode, &version);
  48         if (ret < 0)
  49                 return ret;
  50
  51 -       dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version);
  52 +       dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
  53         *(int *)val = version & SILICON_REVISION_MASK;
  54
  55         return 0;
  56  }
  57
  58 -static struct nvmem_config econfig = {
  59 -       .name = "zynqmp-nvmem",
  60 -       .owner = THIS_MODULE,
  61 -       .word_size = 1,
  62 -       .size = 1,
  63 -       .read_only = true,
  64 -};
  65 -
  66  static const struct of_device_id zynqmp_nvmem_match[] = {
  67         { .compatible = "xlnx,zynqmp-nvmem-fw", },
  68         { /* sentinel */ },
  69 @@ -50,21 +40,18 @@ MODULE_DEVICE_TABLE(of, zynqmp_nvmem_mat
  70  static int zynqmp_nvmem_probe(struct platform_device *pdev)
  71  {
  72         struct device *dev = &pdev->dev;
  73 -       struct zynqmp_nvmem_data *priv;
  74 +       struct nvmem_config econfig = {};
  75
  76 -       priv = devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL);
  77 -       if (!priv)
  78 -               return -ENOMEM;
  79 -
  80 -       priv->dev = dev;
  81 +       econfig.name = "zynqmp-nvmem";
  82 +       econfig.owner = THIS_MODULE;
  83 +       econfig.word_size = 1;
  84 +       econfig.size = 1;
  85         econfig.dev = dev;
  86         econfig.add_legacy_fixed_of_cells = true;
  87 +       econfig.read_only = true;
  88         econfig.reg_read = zynqmp_nvmem_read;
  89 -       econfig.priv = priv;
  90 -
  91 -       priv->nvmem = devm_nvmem_register(dev, &econfig);
  92
  93 -       return PTR_ERR_OR_ZERO(priv->nvmem);
  94 +       return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig));
  95  }
  96
  97  static struct platform_driver zynqmp_nvmem_driver = {