git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 81b0f12a2a8a1699a7d49c3995e5f71e4ec018e6 Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Thu, 27 Oct 2022 14:11:28 +0100
   4 Subject: [PATCH 10/10] net: mtk_eth_soc: add support for in-band 802.3z
   5  negotiation
   6
   7 As a result of help from Frank Wunderlich to investigate and test, we
   8 now know how to program this PCS for in-band 802.3z negotiation. Add
   9 support for this by moving the contents of the two functions into the
  10 common mtk_pcs_config() function and adding the register settings for
  11 802.3z negotiation.
  12
  13 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  14 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  15 ---
  16  drivers/net/ethernet/mediatek/mtk_sgmii.c | 77 ++++++++++++-----------
  17  1 file changed, 42 insertions(+), 35 deletions(-)
  18
  19 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  20 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  21 @@ -33,41 +33,15 @@ static void mtk_pcs_get_state(struct phy
  22                                          FIELD_GET(SGMII_LPA, adv));
  23  }
  24
  25 -/* For SGMII interface mode */
  26 -static void mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
  27 -{
  28 -       regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
  29 -                          SGMII_REMOTE_FAULT_DIS, SGMII_REMOTE_FAULT_DIS);
  30 -
  31 -       regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
  32 -                          SGMII_AN_RESTART, SGMII_AN_RESTART);
  33 -}
  34 -
  35 -/* For 1000BASE-X and 2500BASE-X interface modes, which operate at a
  36 - * fixed speed.
  37 - */
  38 -static void mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
  39 -                                    phy_interface_t interface)
  40 -{
  41 -       /* Disable SGMII AN */
  42 -       regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
  43 -                          SGMII_AN_ENABLE, 0);
  44 -
  45 -       /* Set the speed etc but leave the duplex unchanged */
  46 -       regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
  47 -                          SGMII_IF_MODE_MASK & ~SGMII_DUPLEX_FULL,
  48 -                          SGMII_SPEED_1000);
  49 -}
  50 -
  51  static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
  52                           phy_interface_t interface,
  53                           const unsigned long *advertising,
  54                           bool permit_pause_to_mac)
  55  {
  56         struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
  57 +       unsigned int rgc3, sgm_mode, bmcr;
  58         int advertise, link_timer;
  59 -       unsigned int rgc3;
  60 -       bool changed;
  61 +       bool changed, use_an;
  62
  63         if (interface == PHY_INTERFACE_MODE_2500BASEX)
  64                 rgc3 = RG_PHY_SPEED_3_125G;
  65 @@ -83,6 +57,37 @@ static int mtk_pcs_config(struct phylink
  66         if (link_timer < 0)
  67                 return link_timer;
  68
  69 +       /* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and
  70 +        * we assume that fixes it's speed at bitrate = line rate (in
  71 +        * other words, 1000Mbps or 2500Mbps).
  72 +        */
  73 +       if (interface == PHY_INTERFACE_MODE_SGMII) {
  74 +               sgm_mode = SGMII_IF_MODE_SGMII;
  75 +               if (phylink_autoneg_inband(mode)) {
  76 +                       sgm_mode |= SGMII_REMOTE_FAULT_DIS |
  77 +                                   SGMII_SPEED_DUPLEX_AN;
  78 +                       use_an = true;
  79 +               } else {
  80 +                       use_an = false;
  81 +               }
  82 +       } else if (phylink_autoneg_inband(mode)) {
  83 +               /* 1000base-X or 2500base-X autoneg */
  84 +               sgm_mode = SGMII_REMOTE_FAULT_DIS;
  85 +               use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
  86 +                                          advertising);
  87 +       } else {
  88 +               /* 1000base-X or 2500base-X without autoneg */
  89 +               sgm_mode = 0;
  90 +               use_an = false;
  91 +       }
  92 +
  93 +       if (use_an) {
  94 +               /* FIXME: Do we need to set AN_RESTART here? */
  95 +               bmcr = SGMII_AN_RESTART | SGMII_AN_ENABLE;
  96 +       } else {
  97 +               bmcr = 0;
  98 +       }
  99 +
 100         /* Configure the underlying interface speed */
 101         regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
 102                            RG_PHY_SPEED_3_125G, rgc3);
 103 @@ -94,11 +99,14 @@ static int mtk_pcs_config(struct phylink
 104         /* Setup the link timer and QPHY power up inside SGMIISYS */
 105         regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8);
 106
 107 -       /* Setup SGMIISYS with the determined property */
 108 -       if (interface != PHY_INTERFACE_MODE_SGMII)
 109 -               mtk_pcs_setup_mode_force(mpcs, interface);
 110 -       else if (phylink_autoneg_inband(mode))
 111 -               mtk_pcs_setup_mode_an(mpcs);
 112 +       /* Update the sgmsys mode register */
 113 +       regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
 114 +                          SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN |
 115 +                          SGMII_IF_MODE_SGMII, sgm_mode);
 116 +
 117 +       /* Update the BMCR */
 118 +       regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
 119 +                          SGMII_AN_RESTART | SGMII_AN_ENABLE, bmcr);
 120
 121         /* Release PHYA power down state */
 122         regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
 123 @@ -121,8 +129,7 @@ static void mtk_pcs_link_up(struct phyli
 124         struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
 125         unsigned int sgm_mode;
 126
 127 -       if (!phylink_autoneg_inband(mode) ||
 128 -           phy_interface_mode_is_8023z(interface)) {
 129 +       if (!phylink_autoneg_inband(mode)) {
 130                 /* Force the speed and duplex setting */
 131                 if (speed == SPEED_10)
 132                         sgm_mode = SGMII_SPEED_10;