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1 From 80bbd1c355d661678d2a25bd36e739b6925e7a4e Mon Sep 17 00:00:00 2001
2 From: Luo Jie <quic_luoj@quicinc.com>
3 Date: Wed, 5 Jun 2024 20:45:39 +0800
4 Subject: [PATCH] dt-bindings: clock: add qca8386/qca8084 clock and reset
5 definitions
6
7 QCA8386/QCA8084 includes the clock & reset controller that is
8 accessed by MDIO bus. Two work modes are supported, qca8386 works
9 as switch mode, qca8084 works as PHY mode.
10
11 Reviewed-by: Rob Herring <robh@kernel.org>
12 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
13 Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com
14 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
15 ---
16 .../bindings/clock/qcom,qca8k-nsscc.yaml | 86 +++++++++++++++
17 include/dt-bindings/clock/qcom,qca8k-nsscc.h | 101 ++++++++++++++++++
18 include/dt-bindings/reset/qcom,qca8k-nsscc.h | 76 +++++++++++++
19 3 files changed, 263 insertions(+)
20 create mode 100644 Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
21 create mode 100644 include/dt-bindings/clock/qcom,qca8k-nsscc.h
22 create mode 100644 include/dt-bindings/reset/qcom,qca8k-nsscc.h
23
24 diff --git a/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
25 new file mode 100644
26 index 000000000000..61473385da2d
27 --- /dev/null
28 +++ b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
29 @@ -0,0 +1,86 @@
30 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
31 +%YAML 1.2
32 +---
33 +$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
34 +$schema: http://devicetree.org/meta-schemas/core.yaml#
35 +
36 +title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
37 +
38 +maintainers:
39 + - Bjorn Andersson <andersson@kernel.org>
40 + - Luo Jie <quic_luoj@quicinc.com>
41 +
42 +description: |
43 + Qualcomm NSS clock control module provides the clocks and resets
44 + on QCA8386(switch mode)/QCA8084(PHY mode)
45 +
46 + See also::
47 + include/dt-bindings/clock/qcom,qca8k-nsscc.h
48 + include/dt-bindings/reset/qcom,qca8k-nsscc.h
49 +
50 +properties:
51 + compatible:
52 + oneOf:
53 + - const: qcom,qca8084-nsscc
54 + - items:
55 + - enum:
56 + - qcom,qca8082-nsscc
57 + - qcom,qca8085-nsscc
58 + - qcom,qca8384-nsscc
59 + - qcom,qca8385-nsscc
60 + - qcom,qca8386-nsscc
61 + - const: qcom,qca8084-nsscc
62 +
63 + clocks:
64 + items:
65 + - description: Chip reference clock source
66 + - description: UNIPHY0 RX 312P5M/125M clock source
67 + - description: UNIPHY0 TX 312P5M/125M clock source
68 + - description: UNIPHY1 RX 312P5M/125M clock source
69 + - description: UNIPHY1 TX 312P5M/125M clock source
70 + - description: UNIPHY1 RX 312P5M clock source
71 + - description: UNIPHY1 TX 312P5M clock source
72 +
73 + reg:
74 + items:
75 + - description: MDIO bus address for Clock & Reset Controller register
76 +
77 + reset-gpios:
78 + description: GPIO connected to the chip
79 + maxItems: 1
80 +
81 +required:
82 + - compatible
83 + - clocks
84 + - reg
85 + - reset-gpios
86 +
87 +allOf:
88 + - $ref: qcom,gcc.yaml#
89 +
90 +unevaluatedProperties: false
91 +
92 +examples:
93 + - |
94 + #include <dt-bindings/gpio/gpio.h>
95 + mdio {
96 + #address-cells = <1>;
97 + #size-cells = <0>;
98 +
99 + clock-controller@18 {
100 + compatible = "qcom,qca8084-nsscc";
101 + reg = <0x18>;
102 + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
103 + clocks = <&pcs0_pll>,
104 + <&qca8k_uniphy0_rx>,
105 + <&qca8k_uniphy0_tx>,
106 + <&qca8k_uniphy1_rx>,
107 + <&qca8k_uniphy1_tx>,
108 + <&qca8k_uniphy1_rx312p5m>,
109 + <&qca8k_uniphy1_tx312p5m>;
110 + #clock-cells = <1>;
111 + #reset-cells = <1>;
112 + #power-domain-cells = <1>;
113 + };
114 + };
115 +...
116 diff --git a/include/dt-bindings/clock/qcom,qca8k-nsscc.h b/include/dt-bindings/clock/qcom,qca8k-nsscc.h
117 new file mode 100644
118 index 000000000000..0ac3e4c69a1a
119 --- /dev/null
120 +++ b/include/dt-bindings/clock/qcom,qca8k-nsscc.h
121 @@ -0,0 +1,101 @@
122 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
123 +/*
124 + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
125 + */
126 +
127 +#ifndef _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
128 +#define _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
129 +
130 +#define NSS_CC_SWITCH_CORE_CLK_SRC 0
131 +#define NSS_CC_SWITCH_CORE_CLK 1
132 +#define NSS_CC_APB_BRIDGE_CLK 2
133 +#define NSS_CC_MAC0_TX_CLK_SRC 3
134 +#define NSS_CC_MAC0_TX_DIV_CLK_SRC 4
135 +#define NSS_CC_MAC0_TX_CLK 5
136 +#define NSS_CC_MAC0_TX_SRDS1_CLK 6
137 +#define NSS_CC_MAC0_RX_CLK_SRC 7
138 +#define NSS_CC_MAC0_RX_DIV_CLK_SRC 8
139 +#define NSS_CC_MAC0_RX_CLK 9
140 +#define NSS_CC_MAC0_RX_SRDS1_CLK 10
141 +#define NSS_CC_MAC1_TX_CLK_SRC 11
142 +#define NSS_CC_MAC1_TX_DIV_CLK_SRC 12
143 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC 13
144 +#define NSS_CC_MAC1_SRDS1_CH0_RX_CLK 14
145 +#define NSS_CC_MAC1_TX_CLK 15
146 +#define NSS_CC_MAC1_GEPHY0_TX_CLK 16
147 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK 17
148 +#define NSS_CC_MAC1_RX_CLK_SRC 18
149 +#define NSS_CC_MAC1_RX_DIV_CLK_SRC 19
150 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC 20
151 +#define NSS_CC_MAC1_SRDS1_CH0_TX_CLK 21
152 +#define NSS_CC_MAC1_RX_CLK 22
153 +#define NSS_CC_MAC1_GEPHY0_RX_CLK 23
154 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK 24
155 +#define NSS_CC_MAC2_TX_CLK_SRC 25
156 +#define NSS_CC_MAC2_TX_DIV_CLK_SRC 26
157 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC 27
158 +#define NSS_CC_MAC2_SRDS1_CH1_RX_CLK 28
159 +#define NSS_CC_MAC2_TX_CLK 29
160 +#define NSS_CC_MAC2_GEPHY1_TX_CLK 30
161 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK 31
162 +#define NSS_CC_MAC2_RX_CLK_SRC 32
163 +#define NSS_CC_MAC2_RX_DIV_CLK_SRC 33
164 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC 34
165 +#define NSS_CC_MAC2_SRDS1_CH1_TX_CLK 35
166 +#define NSS_CC_MAC2_RX_CLK 36
167 +#define NSS_CC_MAC2_GEPHY1_RX_CLK 37
168 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK 38
169 +#define NSS_CC_MAC3_TX_CLK_SRC 39
170 +#define NSS_CC_MAC3_TX_DIV_CLK_SRC 40
171 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC 41
172 +#define NSS_CC_MAC3_SRDS1_CH2_RX_CLK 42
173 +#define NSS_CC_MAC3_TX_CLK 43
174 +#define NSS_CC_MAC3_GEPHY2_TX_CLK 44
175 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK 45
176 +#define NSS_CC_MAC3_RX_CLK_SRC 46
177 +#define NSS_CC_MAC3_RX_DIV_CLK_SRC 47
178 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC 48
179 +#define NSS_CC_MAC3_SRDS1_CH2_TX_CLK 49
180 +#define NSS_CC_MAC3_RX_CLK 50
181 +#define NSS_CC_MAC3_GEPHY2_RX_CLK 51
182 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK 52
183 +#define NSS_CC_MAC4_TX_CLK_SRC 53
184 +#define NSS_CC_MAC4_TX_DIV_CLK_SRC 54
185 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC 55
186 +#define NSS_CC_MAC4_SRDS1_CH3_RX_CLK 56
187 +#define NSS_CC_MAC4_TX_CLK 57
188 +#define NSS_CC_MAC4_GEPHY3_TX_CLK 58
189 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK 59
190 +#define NSS_CC_MAC4_RX_CLK_SRC 60
191 +#define NSS_CC_MAC4_RX_DIV_CLK_SRC 61
192 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC 62
193 +#define NSS_CC_MAC4_SRDS1_CH3_TX_CLK 63
194 +#define NSS_CC_MAC4_RX_CLK 64
195 +#define NSS_CC_MAC4_GEPHY3_RX_CLK 65
196 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK 66
197 +#define NSS_CC_MAC5_TX_CLK_SRC 67
198 +#define NSS_CC_MAC5_TX_DIV_CLK_SRC 68
199 +#define NSS_CC_MAC5_TX_SRDS0_CLK 69
200 +#define NSS_CC_MAC5_TX_CLK 70
201 +#define NSS_CC_MAC5_RX_CLK_SRC 71
202 +#define NSS_CC_MAC5_RX_DIV_CLK_SRC 72
203 +#define NSS_CC_MAC5_RX_SRDS0_CLK 73
204 +#define NSS_CC_MAC5_RX_CLK 74
205 +#define NSS_CC_MAC5_TX_SRDS0_CLK_SRC 75
206 +#define NSS_CC_MAC5_RX_SRDS0_CLK_SRC 76
207 +#define NSS_CC_AHB_CLK_SRC 77
208 +#define NSS_CC_AHB_CLK 78
209 +#define NSS_CC_SEC_CTRL_AHB_CLK 79
210 +#define NSS_CC_TLMM_CLK 80
211 +#define NSS_CC_TLMM_AHB_CLK 81
212 +#define NSS_CC_CNOC_AHB_CLK 82
213 +#define NSS_CC_MDIO_AHB_CLK 83
214 +#define NSS_CC_MDIO_MASTER_AHB_CLK 84
215 +#define NSS_CC_SYS_CLK_SRC 85
216 +#define NSS_CC_SRDS0_SYS_CLK 86
217 +#define NSS_CC_SRDS1_SYS_CLK 87
218 +#define NSS_CC_GEPHY0_SYS_CLK 88
219 +#define NSS_CC_GEPHY1_SYS_CLK 89
220 +#define NSS_CC_GEPHY2_SYS_CLK 90
221 +#define NSS_CC_GEPHY3_SYS_CLK 91
222 +#endif
223 diff --git a/include/dt-bindings/reset/qcom,qca8k-nsscc.h b/include/dt-bindings/reset/qcom,qca8k-nsscc.h
224 new file mode 100644
225 index 000000000000..c71167a3bd41
226 --- /dev/null
227 +++ b/include/dt-bindings/reset/qcom,qca8k-nsscc.h
228 @@ -0,0 +1,76 @@
229 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
230 +/*
231 + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
232 + */
233 +
234 +#ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
235 +#define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
236 +
237 +#define NSS_CC_SWITCH_CORE_ARES 1
238 +#define NSS_CC_APB_BRIDGE_ARES 2
239 +#define NSS_CC_MAC0_TX_ARES 3
240 +#define NSS_CC_MAC0_TX_SRDS1_ARES 4
241 +#define NSS_CC_MAC0_RX_ARES 5
242 +#define NSS_CC_MAC0_RX_SRDS1_ARES 6
243 +#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 7
244 +#define NSS_CC_MAC1_TX_ARES 8
245 +#define NSS_CC_MAC1_GEPHY0_TX_ARES 9
246 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 10
247 +#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 11
248 +#define NSS_CC_MAC1_RX_ARES 12
249 +#define NSS_CC_MAC1_GEPHY0_RX_ARES 13
250 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 14
251 +#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 15
252 +#define NSS_CC_MAC2_TX_ARES 16
253 +#define NSS_CC_MAC2_GEPHY1_TX_ARES 17
254 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 18
255 +#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 19
256 +#define NSS_CC_MAC2_RX_ARES 20
257 +#define NSS_CC_MAC2_GEPHY1_RX_ARES 21
258 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 22
259 +#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 23
260 +#define NSS_CC_MAC3_TX_ARES 24
261 +#define NSS_CC_MAC3_GEPHY2_TX_ARES 25
262 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 26
263 +#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 27
264 +#define NSS_CC_MAC3_RX_ARES 28
265 +#define NSS_CC_MAC3_GEPHY2_RX_ARES 29
266 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 30
267 +#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 31
268 +#define NSS_CC_MAC4_TX_ARES 32
269 +#define NSS_CC_MAC4_GEPHY3_TX_ARES 33
270 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 34
271 +#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 35
272 +#define NSS_CC_MAC4_RX_ARES 36
273 +#define NSS_CC_MAC4_GEPHY3_RX_ARES 37
274 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 38
275 +#define NSS_CC_MAC5_TX_ARES 39
276 +#define NSS_CC_MAC5_TX_SRDS0_ARES 40
277 +#define NSS_CC_MAC5_RX_ARES 41
278 +#define NSS_CC_MAC5_RX_SRDS0_ARES 42
279 +#define NSS_CC_AHB_ARES 43
280 +#define NSS_CC_SEC_CTRL_AHB_ARES 44
281 +#define NSS_CC_TLMM_ARES 45
282 +#define NSS_CC_TLMM_AHB_ARES 46
283 +#define NSS_CC_CNOC_AHB_ARES 47
284 +#define NSS_CC_MDIO_AHB_ARES 48
285 +#define NSS_CC_MDIO_MASTER_AHB_ARES 49
286 +#define NSS_CC_SRDS0_SYS_ARES 50
287 +#define NSS_CC_SRDS1_SYS_ARES 51
288 +#define NSS_CC_GEPHY0_SYS_ARES 52
289 +#define NSS_CC_GEPHY1_SYS_ARES 53
290 +#define NSS_CC_GEPHY2_SYS_ARES 54
291 +#define NSS_CC_GEPHY3_SYS_ARES 55
292 +#define NSS_CC_SEC_CTRL_ARES 56
293 +#define NSS_CC_SEC_CTRL_SENSE_ARES 57
294 +#define NSS_CC_SLEEP_ARES 58
295 +#define NSS_CC_DEBUG_ARES 59
296 +#define NSS_CC_GEPHY0_ARES 60
297 +#define NSS_CC_GEPHY1_ARES 61
298 +#define NSS_CC_GEPHY2_ARES 62
299 +#define NSS_CC_GEPHY3_ARES 63
300 +#define NSS_CC_DSP_ARES 64
301 +#define NSS_CC_GEPHY_FULL_ARES 65
302 +#define NSS_CC_GLOBAL_ARES 66
303 +#define NSS_CC_XPCS_ARES 67
304 +#endif
305 --
306 2.45.2
307
Staging tree of Stijn Tintel