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0ce095998f417ef11364b4dbfc27e190426be5ac
[openwrt/staging/ynezz.git] /
1 From fbf296f9ed5daab70020686e9ba072efe663bbab Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 3 Aug 2022 11:14:36 +0800
4 Subject: [PATCH 30/31] tools: mtk_image: add support for nand headers used by
5 newer chips
6
7 This patch adds more nand headers in two new types:
8 1. HSM header, used for spi-nand thru SNFI interface
9 2. SPIM header, used for spi-nand thru spi-mem interface
10
11 The original nand header is renamed to AP header.
12
13 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
14 ---
15 tools/mtk_image.c | 23 ++-
16 tools/mtk_nand_headers.c | 422 +++++++++++++++++++++++++++++++++++++--
17 tools/mtk_nand_headers.h | 110 +++++++++-
18 3 files changed, 525 insertions(+), 30 deletions(-)
19
20 --- a/tools/mtk_image.c
21 +++ b/tools/mtk_image.c
22 @@ -33,6 +33,9 @@ static const struct brom_img_type {
23 }, {
24 .name = "snand",
25 .type = BRLYT_TYPE_SNAND
26 + }, {
27 + .name = "spim-nand",
28 + .type = BRLYT_TYPE_SNAND
29 }
30 };
31
32 @@ -54,7 +57,7 @@ static char lk_name[32] = "U-Boot";
33 static uint32_t crc32tbl[256];
34
35 /* NAND header selected by user */
36 -static const union nand_boot_header *hdr_nand;
37 +static const struct nand_header_type *hdr_nand;
38 static uint32_t hdr_nand_size;
39
40 /* GFH header + 2 * 4KB pages of NAND */
41 @@ -366,20 +369,26 @@ static int mtk_image_verify_nand_header(
42 if (ret < 0)
43 return ret;
44
45 - bh = (struct brom_layout_header *)(ptr + info.page_size);
46 + if (!ret) {
47 + bh = (struct brom_layout_header *)(ptr + info.page_size);
48
49 - if (strcmp(bh->name, BRLYT_NAME))
50 - return -1;
51 + if (strcmp(bh->name, BRLYT_NAME))
52 + return -1;
53 +
54 + if (le32_to_cpu(bh->magic) != BRLYT_MAGIC)
55 + return -1;
56
57 - if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) {
58 - return -1;
59 - } else {
60 if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND)
61 bootmedia = "Parallel NAND";
62 else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND)
63 bootmedia = "Serial NAND (SNFI/AP)";
64 else
65 return -1;
66 + } else {
67 + if (info.snfi)
68 + bootmedia = "Serial NAND (SNFI/HSM)";
69 + else
70 + bootmedia = "Serial NAND (SPIM)";
71 }
72
73 if (print) {
74 --- a/tools/mtk_nand_headers.c
75 +++ b/tools/mtk_nand_headers.c
76 @@ -188,55 +188,346 @@ static const union nand_boot_header nand
77 }
78 };
79
80 -static const struct nand_header_type {
81 +/* HSM BROM NAND header for SPI NAND with 2KB page + 64B spare */
82 +static const union hsm_nand_boot_header hsm_nand_hdr_2k_64_data = {
83 + .data = {
84 + 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
85 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
86 + 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
87 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
88 + 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
89 + 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
90 + 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
91 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
93 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
94 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
95 + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
96 + 0xFF, 0x00, 0x00, 0x00, 0x21, 0xD2, 0xEE, 0xF6,
97 + 0xAE, 0xDD, 0x5E, 0xC2, 0x82, 0x8E, 0x9A, 0x62,
98 + 0x09, 0x8E, 0x80, 0xE2, 0x37, 0x0D, 0xC9, 0xFA,
99 + 0xA9, 0xDD, 0xFC, 0x92, 0x34, 0x2A, 0xED, 0x51,
100 + 0xA4, 0x1B, 0xF7, 0x63, 0xCC, 0x5A, 0xC7, 0xFB,
101 + 0xED, 0x21, 0x02, 0x23, 0x51, 0x31
102 + }
103 +};
104 +
105 +/* HSM BROM NAND header for SPI NAND with 2KB page + 128B spare */
106 +static const union hsm_nand_boot_header hsm_nand_hdr_2k_128_data = {
107 + .data = {
108 + 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
109 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
110 + 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
111 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
112 + 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
113 + 0x40, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00,
114 + 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
115 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
116 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
117 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
118 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
119 + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
120 + 0xFF, 0x00, 0x00, 0x00, 0x71, 0x7f, 0x71, 0xAC,
121 + 0x42, 0xD0, 0x5B, 0xD2, 0x12, 0x81, 0x15, 0x0A,
122 + 0x0C, 0xD4, 0xF6, 0x32, 0x1E, 0x63, 0xE7, 0x81,
123 + 0x8A, 0x7F, 0xDE, 0xF9, 0x4B, 0x91, 0xEC, 0xC2,
124 + 0x70, 0x00, 0x7F, 0x57, 0xAF, 0xDC, 0xE4, 0x24,
125 + 0x57, 0x09, 0xBC, 0xC5, 0x35, 0xDC
126 + }
127 +};
128 +
129 +/* HSM BROM NAND header for SPI NAND with 4KB page + 256B spare */
130 +static const union hsm_nand_boot_header hsm_nand_hdr_4k_256_data = {
131 + .data = {
132 + 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
133 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
134 + 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
135 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
136 + 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
137 + 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
138 + 0x0C, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
139 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
140 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
141 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
142 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
143 + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
144 + 0xFF, 0x00, 0x00, 0x00, 0x62, 0x04, 0xD6, 0x1F,
145 + 0x2B, 0x57, 0x7A, 0x2D, 0xFE, 0xBB, 0x4A, 0x50,
146 + 0xEC, 0xF8, 0x70, 0x1A, 0x44, 0x15, 0xF6, 0xA2,
147 + 0x8E, 0xB0, 0xFD, 0xFA, 0xDC, 0xAA, 0x5A, 0x4E,
148 + 0xCB, 0x8E, 0xC9, 0x72, 0x08, 0xDC, 0x20, 0xB9,
149 + 0x98, 0xC8, 0x82, 0xD8, 0xBE, 0x44
150 + }
151 +};
152 +
153 +/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 64B spare */
154 +static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_64_data = {
155 + .data = {
156 + 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
157 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
158 + 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
159 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
160 + 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
161 + 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
162 + 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
163 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
164 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
165 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
166 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
167 + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
168 + 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
169 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
170 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
171 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
172 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
173 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
174 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
175 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
176 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
177 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
178 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
179 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
180 + 0x5F, 0x4B, 0xB2, 0x5B, 0x8B, 0x1C, 0x35, 0xDA,
181 + 0x83, 0xE6, 0x6C, 0xC3, 0xFB, 0x8C, 0x78, 0x23,
182 + 0xD0, 0x89, 0x24, 0xD9, 0x6C, 0x35, 0x2C, 0x5D,
183 + 0x8F, 0xBB, 0xFC, 0x10, 0xD0, 0xE2, 0x22, 0x7D,
184 + 0xC8, 0x97, 0x9A, 0xEF, 0xC6, 0xB5, 0xA7, 0x4E,
185 + 0x4E, 0x0E
186 + }
187 +};
188 +
189 +/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 128B spare */
190 +static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_128_data = {
191 + .data = {
192 + 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
193 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
194 + 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
195 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
196 + 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
197 + 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
198 + 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
199 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
200 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
201 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
202 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
203 + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
204 + 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
205 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
206 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
207 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
208 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
209 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
210 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
211 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
212 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
213 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
214 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
215 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
216 + 0xF8, 0x7E, 0xC1, 0x5D, 0x61, 0x54, 0xEA, 0x9F,
217 + 0x5E, 0x66, 0x39, 0x66, 0x21, 0xFF, 0x8C, 0x3B,
218 + 0xBE, 0xA7, 0x5A, 0x9E, 0xD7, 0xBD, 0x9E, 0x89,
219 + 0xEE, 0x7E, 0x10, 0x31, 0x9A, 0x1D, 0x82, 0x49,
220 + 0xA3, 0x4E, 0xD8, 0x47, 0xD7, 0x19, 0xF4, 0x2D,
221 + 0x8E, 0x53
222 + }
223 +};
224 +
225 +/* HSM2.0 BROM NAND header for SPI NAND with 4KB page + 256B spare */
226 +static const union hsm20_nand_boot_header hsm20_nand_hdr_4k_256_data = {
227 + .data = {
228 + 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
229 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
230 + 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
231 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
232 + 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
233 + 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
234 + 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
235 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
236 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
237 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
238 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
239 + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
240 + 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
241 + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
242 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
243 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
244 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
245 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
246 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
247 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
248 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
249 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
250 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
251 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
252 + 0x79, 0x01, 0x1F, 0x86, 0x62, 0x6A, 0x43, 0xAE,
253 + 0xE6, 0xF8, 0xDD, 0x5B, 0x29, 0xB7, 0xA2, 0x7F,
254 + 0x29, 0x72, 0x54, 0x37, 0xBE, 0x50, 0xD4, 0x24,
255 + 0xAB, 0x60, 0xF4, 0x44, 0x97, 0x3B, 0x65, 0x21,
256 + 0x73, 0x24, 0x1F, 0x93, 0x0E, 0x9E, 0x96, 0x88,
257 + 0x78, 0x6C
258 + }
259 +};
260 +
261 +/* SPIM-NAND header for SPI NAND with 2KB page + 64B spare */
262 +static const union spim_nand_boot_header spim_nand_hdr_2k_64_data = {
263 + .data = {
264 + 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21,
265 + 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
266 + 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
267 + 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30,
268 + 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
269 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
270 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
271 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
272 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
273 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
274 + }
275 +};
276 +
277 +/* SPIM-NAND header for SPI NAND with 2KB page + 128B spare */
278 +static const union spim_nand_boot_header spim_nand_hdr_2k_128_data = {
279 + .data = {
280 + 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21,
281 + 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
282 + 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
283 + 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30,
284 + 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
285 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
286 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
287 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
288 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
289 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
290 + }
291 +};
292 +
293 +/* SPIM-NAND header for SPI NAND with 4KB page + 256B spare */
294 +static const union spim_nand_boot_header spim_nand_hdr_4k_256_data = {
295 + .data = {
296 + 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21,
297 + 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
298 + 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
299 + 0x40, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x20, 0x30,
300 + 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
301 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
302 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
303 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
304 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
305 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
306 + }
307 +};
308 +
309 +struct nand_header_type {
310 const char *name;
311 - const union nand_boot_header *data;
312 + enum nand_boot_header_type type;
313 + union {
314 + const union nand_boot_header *ap;
315 + const union hsm_nand_boot_header *hsm;
316 + const union hsm20_nand_boot_header *hsm20;
317 + const union spim_nand_boot_header *spim;
318 + };
319 } nand_headers[] = {
320 {
321 .name = "2k+64",
322 - .data = &snand_hdr_2k_64_data
323 + .type = NAND_BOOT_AP_HEADER,
324 + .ap = &snand_hdr_2k_64_data,
325 }, {
326 .name = "2k+120",
327 - .data = &snand_hdr_2k_128_data
328 + .type = NAND_BOOT_AP_HEADER,
329 + .ap = &snand_hdr_2k_128_data,
330 }, {
331 .name = "2k+128",
332 - .data = &snand_hdr_2k_128_data
333 + .type = NAND_BOOT_AP_HEADER,
334 + .ap = &snand_hdr_2k_128_data,
335 }, {
336 .name = "4k+256",
337 - .data = &snand_hdr_4k_256_data
338 + .type = NAND_BOOT_AP_HEADER,
339 + .ap = &snand_hdr_4k_256_data,
340 }, {
341 .name = "1g:2k+64",
342 - .data = &nand_hdr_1gb_2k_64_data
343 + .type = NAND_BOOT_AP_HEADER,
344 + .ap = &nand_hdr_1gb_2k_64_data,
345 }, {
346 .name = "2g:2k+64",
347 - .data = &nand_hdr_2gb_2k_64_data
348 + .type = NAND_BOOT_AP_HEADER,
349 + .ap = &nand_hdr_2gb_2k_64_data,
350 }, {
351 .name = "4g:2k+64",
352 - .data = &nand_hdr_4gb_2k_64_data
353 + .type = NAND_BOOT_AP_HEADER,
354 + .ap = &nand_hdr_4gb_2k_64_data,
355 }, {
356 .name = "2g:2k+128",
357 - .data = &nand_hdr_2gb_2k_128_data
358 + .type = NAND_BOOT_AP_HEADER,
359 + .ap = &nand_hdr_2gb_2k_128_data,
360 }, {
361 .name = "4g:2k+128",
362 - .data = &nand_hdr_4gb_2k_128_data
363 + .type = NAND_BOOT_AP_HEADER,
364 + .ap = &nand_hdr_4gb_2k_128_data,
365 + }, {
366 + .name = "hsm:2k+64",
367 + .type = NAND_BOOT_HSM_HEADER,
368 + .hsm = &hsm_nand_hdr_2k_64_data,
369 + }, {
370 + .name = "hsm:2k+128",
371 + .type = NAND_BOOT_HSM_HEADER,
372 + .hsm = &hsm_nand_hdr_2k_128_data,
373 + }, {
374 + .name = "hsm:4k+256",
375 + .type = NAND_BOOT_HSM_HEADER,
376 + .hsm = &hsm_nand_hdr_4k_256_data,
377 + }, {
378 + .name = "hsm20:2k+64",
379 + .type = NAND_BOOT_HSM20_HEADER,
380 + .hsm20 = &hsm20_nand_hdr_2k_64_data,
381 + }, {
382 + .name = "hsm20:2k+128",
383 + .type = NAND_BOOT_HSM20_HEADER,
384 + .hsm20 = &hsm20_nand_hdr_2k_128_data,
385 + }, {
386 + .name = "hsm20:4k+256",
387 + .type = NAND_BOOT_HSM20_HEADER,
388 + .hsm20 = &hsm20_nand_hdr_4k_256_data,
389 + }, {
390 + .name = "spim:2k+64",
391 + .type = NAND_BOOT_SPIM_HEADER,
392 + .spim = &spim_nand_hdr_2k_64_data,
393 + }, {
394 + .name = "spim:2k+128",
395 + .type = NAND_BOOT_SPIM_HEADER,
396 + .spim = &spim_nand_hdr_2k_128_data,
397 + }, {
398 + .name = "spim:4k+256",
399 + .type = NAND_BOOT_SPIM_HEADER,
400 + .spim = &spim_nand_hdr_4k_256_data,
401 }
402 };
403
404 -const union nand_boot_header *mtk_nand_header_find(const char *name)
405 +const struct nand_header_type *mtk_nand_header_find(const char *name)
406 {
407 uint32_t i;
408
409 for (i = 0; i < ARRAY_SIZE(nand_headers); i++) {
410 if (!strcmp(nand_headers[i].name, name))
411 - return nand_headers[i].data;
412 + return &nand_headers[i];
413 }
414
415 return NULL;
416 }
417
418 -uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand)
419 +uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand)
420 {
421 - return 2 * le16_to_cpu(hdr_nand->pagesize);
422 + switch (hdr_nand->type) {
423 + case NAND_BOOT_HSM_HEADER:
424 + return le32_to_cpu(hdr_nand->hsm->page_size);
425 +
426 + case NAND_BOOT_HSM20_HEADER:
427 + return le32_to_cpu(hdr_nand->hsm20->page_size);
428 +
429 + case NAND_BOOT_SPIM_HEADER:
430 + return le32_to_cpu(hdr_nand->spim->page_size);
431 +
432 + default:
433 + return 2 * le16_to_cpu(hdr_nand->ap->pagesize);
434 + }
435 }
436
437 static int mtk_nand_header_ap_info(const void *ptr,
438 @@ -251,14 +542,45 @@ static int mtk_nand_header_ap_info(const
439 info->page_size = le16_to_cpu(nh->pagesize);
440 info->spare_size = le16_to_cpu(nh->oobsize);
441 info->gfh_offset = 2 * info->page_size;
442 + info->snfi = true;
443
444 return 0;
445 }
446
447 +static int mtk_nand_header_hsm_info(const void *ptr,
448 + struct nand_header_info *info)
449 +{
450 + union hsm_nand_boot_header *nh = (union hsm_nand_boot_header *)ptr;
451 +
452 + info->page_size = le16_to_cpu(nh->page_size);
453 + info->spare_size = le16_to_cpu(nh->spare_size);
454 + info->gfh_offset = info->page_size;
455 + info->snfi = true;
456 +
457 + return 1;
458 +}
459 +
460 +static int mtk_nand_header_spim_info(const void *ptr,
461 + struct nand_header_info *info)
462 +{
463 + union spim_nand_boot_header *nh = (union spim_nand_boot_header *)ptr;
464 +
465 + info->page_size = le16_to_cpu(nh->page_size);
466 + info->spare_size = le16_to_cpu(nh->spare_size);
467 + info->gfh_offset = info->page_size;
468 + info->snfi = false;
469 +
470 + return 1;
471 +}
472 +
473 int mtk_nand_header_info(const void *ptr, struct nand_header_info *info)
474 {
475 if (!strcmp((char *)ptr, NAND_BOOT_NAME))
476 return mtk_nand_header_ap_info(ptr, info);
477 + else if (!strncmp((char *)ptr, HSM_NAND_BOOT_NAME, 8))
478 + return mtk_nand_header_hsm_info(ptr, info);
479 + else if (!strncmp((char *)ptr, SPIM_NAND_BOOT_NAME, 8))
480 + return mtk_nand_header_spim_info(ptr, info);
481
482 return -1;
483 }
484 @@ -273,14 +595,74 @@ bool is_mtk_nand_header(const void *ptr)
485 return false;
486 }
487
488 -uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr)
489 +static uint16_t crc16(const uint8_t *p, uint32_t len)
490 +{
491 + uint16_t crc = 0x4f4e;
492 + uint32_t i;
493 +
494 + while (len--) {
495 + crc ^= *p++ << 8;
496 + for (i = 0; i < 8; i++)
497 + crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
498 + }
499 +
500 + return crc;
501 +}
502 +
503 +static uint32_t mtk_nand_header_put_ap(const struct nand_header_type *hdr_nand,
504 + void *ptr)
505 {
506 - union nand_boot_header *nh = (union nand_boot_header *)ptr;
507 int i;
508
509 /* NAND device header, repeat 4 times */
510 - for (i = 0; i < 4; i++)
511 - memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header));
512 + for (i = 0; i < 4; i++) {
513 + memcpy(ptr, hdr_nand->ap, sizeof(*hdr_nand->ap));
514 + ptr += sizeof(*hdr_nand->ap);
515 + }
516 +
517 + return le16_to_cpu(hdr_nand->ap->pagesize);
518 +}
519
520 - return le16_to_cpu(hdr_nand->pagesize);
521 +static uint32_t mtk_nand_header_put_hsm(const struct nand_header_type *hdr_nand,
522 + void *ptr)
523 +{
524 + memcpy(ptr, hdr_nand->hsm, sizeof(*hdr_nand->hsm));
525 + return 0;
526 +}
527 +
528 +static uint32_t mtk_nand_header_put_hsm20(const struct nand_header_type *hdr_nand,
529 + void *ptr)
530 +{
531 + memcpy(ptr, hdr_nand->hsm20, sizeof(*hdr_nand->hsm20));
532 + return 0;
533 +}
534 +
535 +static uint32_t mtk_nand_header_put_spim(const struct nand_header_type *hdr_nand,
536 + void *ptr)
537 +{
538 + uint16_t crc;
539 +
540 + memcpy(ptr, hdr_nand->spim, sizeof(*hdr_nand->spim));
541 +
542 + crc = crc16(ptr, 0x4e);
543 + memcpy(ptr + 0x4e, &crc, sizeof(uint16_t));
544 +
545 + return 0;
546 +}
547 +
548 +uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, void *ptr)
549 +{
550 + switch (hdr_nand->type) {
551 + case NAND_BOOT_HSM_HEADER:
552 + return mtk_nand_header_put_hsm(hdr_nand, ptr);
553 +
554 + case NAND_BOOT_HSM20_HEADER:
555 + return mtk_nand_header_put_hsm20(hdr_nand, ptr);
556 +
557 + case NAND_BOOT_SPIM_HEADER:
558 + return mtk_nand_header_put_spim(hdr_nand, ptr);
559 +
560 + default:
561 + return mtk_nand_header_put_ap(hdr_nand, ptr);
562 + }
563 }
564 --- a/tools/mtk_nand_headers.h
565 +++ b/tools/mtk_nand_headers.h
566 @@ -16,6 +16,7 @@ struct nand_header_info {
567 uint32_t page_size;
568 uint32_t spare_size;
569 uint32_t gfh_offset;
570 + bool snfi;
571 };
572
573 /* AP BROM Header for NAND */
574 @@ -39,15 +40,117 @@ union nand_boot_header {
575 uint8_t data[0x80];
576 };
577
578 +/* HSM BROM Header for NAND */
579 +union hsm_nand_boot_header {
580 + struct {
581 + char id[8];
582 + uint32_t version; /* Header version */
583 + uint32_t config; /* Header config */
584 + uint32_t sector_size; /* ECC step size */
585 + uint32_t fdm_size; /* User OOB size of a step */
586 + uint32_t fdm_ecc_size; /* ECC parity size of a step */
587 + uint32_t lbs;
588 + uint32_t page_size; /* NAND page size */
589 + uint32_t spare_size; /* NAND page spare size */
590 + uint32_t page_per_block; /* Pages of one block */
591 + uint32_t blocks; /* Total blocks of NAND chip */
592 + uint32_t plane_sel_position; /* Plane bit position */
593 + uint32_t pll; /* Value of pll reg */
594 + uint32_t acccon; /* Value of access timing reg */
595 + uint32_t strobe_sel; /* Value of DQS selection reg*/
596 + uint32_t acccon1; /* Value of access timing reg */
597 + uint32_t dqs_mux; /* Value of DQS mux reg */
598 + uint32_t dqs_ctrl; /* Value of DQS control reg */
599 + uint32_t delay_ctrl; /* Value of delay ctrl reg */
600 + uint32_t latch_lat; /* Value of latch latency reg */
601 + uint32_t sample_delay; /* Value of sample delay reg */
602 + uint32_t driving; /* Value of driving reg */
603 + uint32_t bl_start; /* Bootloader start addr */
604 + uint32_t bl_end; /* Bootloader end addr */
605 + uint8_t ecc_parity[42]; /* ECC parity of this header */
606 + };
607 +
608 + uint8_t data[0x8E];
609 +};
610 +
611 +/* HSM2.0 BROM Header for NAND */
612 +union hsm20_nand_boot_header {
613 + struct {
614 + char id[8];
615 + uint32_t version; /* Header version */
616 + uint32_t config; /* Header config */
617 + uint32_t sector_size; /* ECC step size */
618 + uint32_t fdm_size; /* User OOB size of a step */
619 + uint32_t fdm_ecc_size; /* ECC parity size of a step */
620 + uint32_t lbs;
621 + uint32_t page_size; /* NAND page size */
622 + uint32_t spare_size; /* NAND page spare size */
623 + uint32_t page_per_block; /* Pages of one block */
624 + uint32_t blocks; /* Total blocks of NAND chip */
625 + uint32_t plane_sel_position; /* Plane bit position */
626 + uint32_t pll; /* Value of pll reg */
627 + uint32_t acccon; /* Value of access timing reg */
628 + uint32_t strobe_sel; /* Value of DQS selection reg*/
629 + uint32_t acccon1; /* Value of access timing reg */
630 + uint32_t dqs_mux; /* Value of DQS mux reg */
631 + uint32_t dqs_ctrl; /* Value of DQS control reg */
632 + uint32_t delay_ctrl; /* Value of delay ctrl reg */
633 + uint32_t latch_lat; /* Value of latch latency reg */
634 + uint32_t sample_delay; /* Value of sample delay reg */
635 + uint32_t driving; /* Value of driving reg */
636 + uint32_t reserved;
637 + uint32_t bl0_start; /* Bootloader start addr */
638 + uint32_t bl0_end; /* Bootloader end addr */
639 + uint32_t bl0_type; /* Bootloader type */
640 + uint8_t bl_reserve[84];
641 + uint8_t ecc_parity[42]; /* ECC parity of this header */
642 + };
643 +
644 + uint8_t data[0xEA];
645 +};
646 +
647 +/* SPIM BROM Header for SPI-NAND */
648 +union spim_nand_boot_header {
649 + struct {
650 + char id[8];
651 + uint32_t version; /* Header version */
652 + uint32_t config; /* Header config */
653 + uint32_t page_size; /* NAND page size */
654 + uint32_t spare_size; /* NAND page spare size */
655 + uint16_t page_per_block; /* Pages of one block */
656 + uint16_t plane_sel_position; /* Plane bit position */
657 + uint16_t reserve_reg;
658 + uint16_t reserve_val;
659 + uint16_t ecc_error; /* ECC error reg addr */
660 + uint16_t ecc_mask; /* ECC error bit mask */
661 + uint32_t bl_start; /* Bootloader start addr */
662 + uint32_t bl_end; /* Bootloader end addr */
663 + uint8_t ecc_parity[32]; /* ECC parity of this header */
664 + uint32_t integrity_crc; /* CRC of this header */
665 + };
666 +
667 + uint8_t data[0x50];
668 +};
669 +
670 +enum nand_boot_header_type {
671 + NAND_BOOT_AP_HEADER,
672 + NAND_BOOT_HSM_HEADER,
673 + NAND_BOOT_HSM20_HEADER,
674 + NAND_BOOT_SPIM_HEADER
675 +};
676 +
677 #define NAND_BOOT_NAME "BOOTLOADER!"
678 #define NAND_BOOT_VERSION "V006"
679 #define NAND_BOOT_ID "NFIINFO"
680
681 +#define HSM_NAND_BOOT_NAME "NANDCFG!"
682 +#define SPIM_NAND_BOOT_NAME "SPINAND!"
683 +
684 /* Find nand header data by name */
685 -const union nand_boot_header *mtk_nand_header_find(const char *name);
686 +const struct nand_header_type *mtk_nand_header_find(const char *name);
687
688 /* Device header size using this nand header */
689 -uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand);
690 +uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand);
691
692 /* Get nand info from nand header (page size, spare size, ...) */
693 int mtk_nand_header_info(const void *ptr, struct nand_header_info *info);
694 @@ -56,6 +159,7 @@ int mtk_nand_header_info(const void *ptr
695 bool is_mtk_nand_header(const void *ptr);
696
697 /* Generate Device header using give nand header */
698 -uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr);
699 +uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand,
700 + void *ptr);
701
702 #endif /* _MTK_NAND_HEADERS_H */
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